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IT8673F advanced input / outpu t (advanced i/o) preliminary specification v0.5
copyright ? 2002 ite, inc. this is preliminary document release. all specifications are subject to change without notice. the material contained in this document supersedes all previous documentation issued for the related products included herein. please contact ite, inc. for the latest document(s). all sales are subject to ite?s standard terms and conditions, a copy of which is included in the back of this document. ite, IT8673F is a trademark of ite, inc. intel, pentium, and mmx are claimed as trademarks by intel corp. cyrix, m1, and slic/mp are claimed as trademarks by cyrix corp. amd, amd-k5, and amd-k6 are claimed as trademarks by advanced micro devices, inc. microsoft and windows are claimed as trademarks by microsoft corporation. pci is claimed as a trademark by the pci special interest group. irda is claimed as a trademark by the infrared data association. all other trademarks are claimed by their respective owners. all specifications are subject to change without notice. additional copies of this manual or other ite literature may be obtained from: ite, inc. phone: (02) 2912-6889 marketing department fax: (02) 2910-2551, 2910-2552 8f, no. 233-1, bao chiao rd., hsin tien taipei county 231, taiwan, r.o.c. ite (usa) inc. phone: (408) 530-8860 marketing department fax: (408) 530-8861 1235 midas way sunnyvale, ca 94086 u.s.a. ite (usa) inc. phone: (512) 388-7880 eastern u.s.a. sales office fax: (512) 388-3108 896 summit st., #105 round rock, tx 78664 u.s.a. if you have any marketing or sales questions, please contact: lawrence liu , at ite taiwan: e-mail: lawrence.liu@ite.com.tw , tel: 886-2-29126889 x6071, fax: 886-2-29102551 david lin , at ite u.s.a: e-mail: david.lin@iteusa.com , tel: (408) 980-8168 x238, fax: (408) 980-9232 don gardenhire , at ite eastern usa office: e-mail: don.gardenhire@iteusa.com , tel: (512) 388-7880, fax: (512) 388-3108 to find out more about ite, visit our world wide web at: http://www.ite.com.tw http://www.iteusa.com or e-mail itesupport@ite.com.tw for more product information/services.
1 revision history section revision page no. the content of the copyright page has been revised.
i contents page 1. features .................................................................................................................... ................................... 1 2. general description ......................................................................................................... ........................... 2 3. block diagram ............................................................................................................... .............................. 3 4. pinout table................................................................................................................ ................................. 4 5. pin configuration ........................................................................................................... ............................. 5 6. IT8673F pin descriptions .................................................................................................... ....................... 6 7. special pin routings ........................................................................................................ ........................ 11 8. list of gpio pins........................................................................................................... ............................ 12 9. power on strapping options.................................................................................................. ................. 13 10. configuration.............................................................................................................. ............................... 14 10.1 configuring sequence description .......................................................................................... ...........14 10.2 description of the configuration registers ................................................................................ .........16 10.2.1 logical device base address ............................................................................................. ......... 20 10.3 global configuration registers (ldn: all) ................................................................................. .........21 10.3.1 configure control (index=02h) ........................................................................................... ......... 21 10.3.2 logical device number (ldn, index=07h) .................................................................................. 21 10.3.3 chip id byte 1 (index=20h, default=86h)................................................................................. ... 21 10.3.4 chip id byte 2 (index=21h, default=73h)................................................................................. ... 21 10.3.5 chip version (index=22h, default=01h) ................................................................................... ... 21 10.3.6 clock selection register (index=23h, default=00h).................................................................... 21 10.3.7 software suspend (index=24h, default=00h, mb pnp) .............................................................. 21 10.3.8 gpio multi-function pin selection register (index=25h, default=00h)...................................... 22 10.3.9 reserved register (index=26h, default=00h) ............................................................................. 2 2 10.3.10 reserved register (index=27h, default=00h) ............................................................................. 22 10.3.11 reserved register (index=28h, default=00h) ............................................................................. 22 10.3.12 reserved register (index=29h, default=00h) ............................................................................. 22 10.3.13 test 1 register (index=2eh, default=00h) ............................................................................... ... 22 10.3.14 test 2 register (index=2fh, default=00h) ............................................................................... ... 22 10.4 fdc configuration registers (ldn=00h) ..................................................................................... ......22 10.4.1 fdc activate (index=30h, default=00h)................................................................................... ... 22 10.4.2 fdc base address msb register (index=60h, default=03h)..................................................... 23 10.4.3 fdc base address lsb register (index=61h, default=f0h) ..................................................... 23 10.4.4 fdc interrupt level select (index=70h, default=06h) ................................................................ 23 10.4.5 fdc dma channel select (index=74h, default=02h) ................................................................. 23 10.4.6 fdc special configuration register (index=f0h, default=00h) ................................................. 23 10.5 serial port 1 configuration registers (ldn=01h)........................................................................... ....23 10.5.1 serial port 1 activate (index=30h, default=00h) ......................................................................... 23 10.5.2 serial port 1 base address msb register (index=60h, default=03h) .. ........................................ 24
ii 10.5.3 serial port 1 base address lsb register (index=61h, default=f8h).. ......................................... 24 10.5.4 serial port 1 interrupt level select (index=70h, default=04h).................................................... 24 10.5.5 serial port 1 special configuration register (index=f0h, default=00h) ..................................... 24 10.6 serial port 2 configuration registers (ldn=02h)........................................................................... ....24 10.6.1 serial port 2 activate (index=30h, default=00h) ......................................................................... 24 10.6.2 serial port 2 base address msb register (index=60h, default=02h) .. ........................................ 25 10.6.3 serial port 2 base address lsb register (index=61h, default=f8h).. ......................................... 25 10.6.4 consumer ir base address msb register (index=62h, default=03h).. ....................................... 25 10.6.5 consumer ir base address lsb register (index=63h, default=00h).. ........................................ 25 10.6.6 serial port 2 interrupt level select (index=70h, default=03h).................................................... 25 10.6.7 consumer ir interrupt level select (index=72h, default=00h) .................................................. 25 10.6.8 serial port 2 special configuration register 1 (index=f0h, default=00h) .................................. 26 10.6.9 serial port 2 special configuration register 2 (index=f1h, default=40h) .................................. 26 10.7 parallel port configuration registers (ldn=03h) ........................................................................... ....26 10.7.1 parallel port activate (index=30h, default=00h) ......................................................................... 26 10.7.2 parallel port primary base address msb register (index=60h, default=03h)............................. 26 10.7.3 parallel port primary base address lsb register (index=61h, default=78h) ............................ 27 10.7.4 parallel port secondary base address msb register (index=62h, default=07h).. ...................... 27 10.7.5 parallel port secondary base address lsb register (index=63h, default=78h) ....................... 27 10.7.6 parallel port interrupt level select (index =70h, default=07h) ................................................... 27 10.7.7 parallel port dma channel select (index=74h, default=03h)..................................................... 27 10.7.8 parallel port special configuration register (index=f0h, default=03h) ..................................... 27 10.8 fan controller configuration registers (ldn=04h).......................................................................... .28 10.8.1 fan controller activate register (index=30h, default=00h)....................................................... 28 10.8.2 fan controller base address msb register (index=60h, default=00h).. .................................... 28 10.8.3 fan controller base address lsb register (index=61h, default=80h).. ..................................... 28 10.8.4 pme# direct access base address msb register (index=62h, default=02h)............................. 28 10.8.5 pme# direct access base address lsb register (index=63h, default=00h).............................. 28 10.8.6 fan controller interrupt level select (index=70h, default=09h)................................................ 28 10.8.7 apc/pme# event enable register (per) (index=f0h, default=00h)......................................... 29 10.8.8 apc/pme# status register (psr) (index=f1h, default=00h).................................................... 29 10.8.9 apc/pme# control register 1 (pcr 1) (index=f2h, default=00h) ............................................ 30 10.8.10 fan controller special configuration register (index=f3h, default=00h) ................................. 30 10.8.11 apc/pme# control register 2 (pcr 2) (index=f4h, default=00h) ............................................ 30 10.8.12 apc/pme# special code index register (index=f5h) ............................................................... 31 10.8.13 apc/pme# special code data register (index=f6h) ................................................................ 31 10.9 kbc (keyboard) configuration registers (ldn=05h) .........................................................................3 1 10.9.1 kbc (keyboard) activate (index=30h, default=01h or 00h) ........................................................ 31 10.9.2 kbc (keyboard) data base address msb register (index=60h, default=00h).......................... 31 10.9.3 kbc (keyboard) data base address lsb register (index=61h, default=60h)........................... 31 10.9.4 kbc (keyboard) command base address msb register (index=62h, default=00h)................. 31 10.9.5 kbc (keyboard) command base address lsb register (index=63h, default=64h).................. 31
iii 10.9.6 kbc (keyboard) interrupt level select (index=70h, default=01h) .............................................. 32 10.9.7 kbc (keyboard) interrupt type (index=71h, default=02h).......................................................... 32 10.9.8 kbc (keyboard) special configuration register (index=f0h, default=00h).................................... 32 10.10 kbc (mouse) configuration registers (ldn=06h) ............................................................................ .32 10.10.1 kbc (mouse) activate (index=30h, default=00h) ....................................................................... 32 10.10.2 kbc (mouse) interrupt level select (index=70h, default=0ch)..................................................... 32 10.10.3 kbc (mouse) interrupt type (index=71h, default=02h).............................................................. 33 10.10.4 kbc (mouse) special configuration register (index=f0h, default=00h) ................................... 33 10.11 gpio configuration registers (ldn=07h)................................................................................... .......33 10.11.1 cs0 base address msb register (index=60h, default=00h) ..................................................... 33 10.11.2 cs0 base address lsb register (index=61h, default=00h) ...................................................... 33 10.11.3 cs1 base address msb register (index=62h, default=00h) ..................................................... 33 10.11.4 cs1 base address lsb register (index=63h, default=00h) ...................................................... 33 10.11.5 cs2 base address msb register (index=64h, default=00h) ..................................................... 34 10.11.6 cs2 base address lsb register (index=65h, default=00h) ...................................................... 34 10.11.7 simple i/o base address msb register (index=66h, default=00h) ........................................... 34 10.11.8 simple i/o base address lsb register (index=67h, default=00h) ............................................ 34 10.11.9 panel button de-bounce base address msb register (index=68h, default=00h)..................... 34 10.11.10 panel button de-bounce base address lsb register (index=69h, default=00h) .................. 34 10.11.11 gp irq steering 1 control register (index=70h, default=00h) .............................................. 35 10.11.12 gp irq steering 1 pin mapping register (index=71h, default=00h)...................................... 35 10.11.13 gp irq steering 2 control register (index=72h, default=00h) .............................................. 35 10.11.14 gp irq steering 2 pin mapping register (index=73h, default=00h)...................................... 35 10.11.15 gp set selection register (index=f0h, default=00h) ............................................................. 35 10.11.16 csx pin mapping register (index=f1h, default=00h) ............................................................ 35 10.11.17 csx control register (index=f2h, default=00h)..................................................................... 36 10.11.18 gpio pin polarity register (index=f3h, default=00h) ............................................................ 36 10.11.19 gpio pin internal pull-up enable register (index=f4h, default=00h).................................... 36 10.11.20 simple i/o enable register (index=f5h, default=00h)............................................................ 36 10.11.21 simple i/o direction selection register (index=f6h, default=00h)......................................... 37 10.11.22 panel button de-bounce enable register (index=f7h, default=00h) ..................................... 37 10.11.23 panel button de-bounce control register/gp led blinking 2 control register (index=f8h, default=00h) ....................................................................................................... .37 10.11.24 keyboard lock pin mapping register (index=f9h, default=00h) ........................................... 37 10.11.25 gp led blinking 1 pin mapping register (index=fah, default=00h) ..................................... 38 10.11.26 gp led blinking control and ring# pin mapping register (index=fbh, default=00h) ........ 38 10.11.27 gp led blinking 2 pin mapping register (index=fch, default= 00h) ...................................... 38 10.11.28 reserved register (index=fdh, default=00h)......................................................................... 38 10.11.29 pci clkrun# pin mapping register (index=feh, default=00h) ........................................... 38 10.11.30 smi# pin mapping register (index=ffh, default=00h) ........................................................... 39 10.11.31 smi# control register 1 (index=e0h, default=00h) ................................................................ 39 10.11.32 smi# control register 2 (index=e1h, default=00h) ................................................................ 39
iv 10.11.33 smi# status register 1 (index=e2h, default=00h).................................................................. 39 10.11.34 smi# status register 2 (index=e3h, default=00h).................................................................. 40 11. functional description ..................................................................................................... ........................ 41 11.1 general purpose i/o ....................................................................................................... ....................41 11.2 advanced power supply control and pme# .................................................................................... ..42 11.3 fan controller ............................................................................................................ ........................42 11.3.1 interfaces .............................................................................................................. ....................... 43 11.3.2 registers............................................................................................................... ....................... 43 11.3.3 operation ............................................................................................................... ...................... 47 11.4 floppy disk controller (fdc) .............................................................................................. ................47 11.4.1 introduction ............................................................................................................ ...................... 47 11.4.2 reset................................................................................................................... ......................... 47 11.4.3 hardware reset (reset pin) .............................................................................................. ....... 48 11.4.4 software reset (dor reset and dsr reset) ............................................................................ 48 11.4.5 digital data separator .................................................................................................. ............... 48 11.4.6 write precompensation ................................................................................................... ............ 48 11.4.7 data rate selection ..................................................................................................... ................ 48 11.4.8 status, data and control registers ...................................................................................... ....... 48 11.4.9 controller phases ....................................................................................................... ................. 52 11.4.10 command set ............................................................................................................ .................. 56 11.4.11 data transfer commands ................................................................................................. .......... 66 11.4.12 control commands ....................................................................................................... ............... 69 11.4.13 dma transfers.......................................................................................................... ................... 73 11.4.14 low power mode ......................................................................................................... ................ 73 11.5 serial port (uart) description ............................................................................................ ...............74 11.5.1 data registers .......................................................................................................... ................... 74 11.5.2 control registers: ier, iir, fcr, dll, dlm, lcr and mcr ..................................................... 74 11.5.3 status registers: lsr and msr ........................................................................................... ...... 81 11.5.4 reset................................................................................................................... ......................... 83 11.5.5 programming ............................................................................................................. .................. 83 11.5.6 software reset .......................................................................................................... .................. 83 11.5.7 clock input operation ................................................................................................... ............... 83 11.5.8 fifo interrupt mode operation ........................................................................................... ........ 83 11.6 parallel port............................................................................................................. ............................85 11.6.1 spp and epp modes....................................................................................................... ............ 86 11.6.2 epp operation ........................................................................................................... .................. 87 11.6.3 ecp mode................................................................................................................ .................... 88 11.7 keyboard controller (kbc) ................................................................................................. ................96 11.7.1 host interface.......................................................................................................... ..................... 96 11.7.2 data registers and status register ...................................................................................... ...... 97 11.7.3 keyboard and mouse interface............................................................................................ ........ 97 11.7.4 kirq and mirq........................................................................................................... ................ 97
v 11.8 consumer remote control (tv remote) ir (cir) .............................................................................9 8 11.8.1 overview ................................................................................................................ ...................... 98 11.8.2 features................................................................................................................ ....................... 98 11.8.3 block diagram........................................................................................................... ................... 98 11.8.4 transmit operation ...................................................................................................... ................ 99 11.8.5 receive operation ....................................................................................................... ................ 99 11.8.6 register descriptions and address ....................................................................................... ...... 99 12. dc electrical characteristics.............................................................................................. ................... 108 13. ac characteristics (vcc = 5v 5%, ta = 0 c to + 70 c) .................................................................... 110 13.1 clock input timings....................................................................................................... ....................110 13.2 pciclk and reset timings .................................................................................................. .........110 13.3 cpu read cycle timings .................................................................................................... .............111 13.4 cpu write cycle timings................................................................................................... ...............111 13.5 serirq timings............................................................................................................ ...................112 13.6 dma timings............................................................................................................... ......................112 13.7 floppy disk drive timings ................................................................................................. ...............113 13.8 serial port, askir, sir and consumer remote control timings....................................................114 13.9 modem control timings ..................................................................................................... ...............114 13.10 epp address or data write cycle timings.................................................................................. .....115 13.11 epp address or data read cycle timings................................................................................... ....115 13.12 ecp parallel port forward timings ........................................................................................ ..........116 13.13 ecp parallel port backward timings....................................................................................... .........116 14. package information........................................................................................................ ....................... 117 15. ordering information ....................................................................................................... ....................... 118 tables table 6-1. signal names (by pin numbers in alphabetical order) ................................................................. ...... 6 table 8-1. general purpose i/o ................................................................................................. ....................... 12 table 9-1. power on strapping .................................................................................................. ....................... 13 table 10-1. global configuration registers ..................................................................................... ................. 16 table 10-2. fdc configuration registers ........................................................................................ ................. 16 table 10-3. serial port 1 configuration registers.............................................................................. ............... 16 table 10-4. serial port 2 configuration registers.............................................................................. ............... 17 table 10-5. parallel port configuration registers .............................................................................. ............... 17 table 10-6. fan controller configuration registers............................................................................. ............ 17 table 10-7. kbc(keyboard) configuration registers .............................................................................. ......... 18 table 10-8. kbc(mouse) configuration registers ................................................................................. ........... 18 table 10-9. gpio configuration registers....................................................................................... ................. 18 table 10-10. base address of logical devices................................................................................... .............. 20 table 11-1. address map on the isa bus ......................................................................................... ................ 43 table 11-2. fan controller registers ........................................................................................... .................... 44
vi table 11-3. digital output register (dor)...................................................................................... .................. 49 table 11-4. tape drive register (tdr) .......................................................................................... .................. 49 table 11-5. main status register (msr) ......................................................................................... ................. 50 table 11-6. data rate select register (dsr).................................................................................... ............... 51 table 11-7. data register (fifo)............................................................................................... ....................... 51 table 11-8. digital input register (dir) ....................................................................................... ..................... 52 table 11-9. diskette control register (dcr) .................................................................................... ................ 52 table 11-10. status register 0 (st0)........................................................................................... ..................... 53 table 11-11. status register 1 (st1)........................................................................................... ..................... 54 table 11-12. status register 2 (st2)........................................................................................... ..................... 55 table 11-13. status register 3 (st3)........................................................................................... ..................... 55 table 11-14. command set symbol descriptions ................................................................................... ......... 56 table 11-15. command set summary............................................................................................... ............... 58 table 11-16. effects of mt and n bits .......................................................................................... .................... 66 table 11-17. scan command result ............................................................................................... ............... 68 table 11-18. verify command result ............................................................................................. .............. 69 table 11-19. interrupt identification.......................................................................................... ......................... 71 table 11-20. hut values ........................................................................................................ .......................... 71 table 11-21. srt values ........................................................................................................ .......................... 72 table 11-22. hlt values........................................................................................................ ........................... 72 table 11-23. effects of gap and wg on format a track and write data commands........................ 72 table 11-24. effects of drive mode and data rate on format a track and write data commands... 73 table 11-25. serial channel registers .......................................................................................... ................... 74 table 11-26. interrupt enable register description ............................................................................. ............. 75 table 11-27. interrupt identification register ................................................................................. ................... 76 table 11-28. fifo control register description ................................................................................. .............. 77 table 11-29. receiver fifo trigger level encoding.............................................................................. .......... 77 table 11-30. baud rates using (24 mhz 13) clock....................................................................................... 78 table 11-31. line control register description ................................................................................. ............... 79 table 11-32. stop bits number encoding ......................................................................................... ................ 79 table 11-33. modem control register description ................................................................................ ........... 80 table 11-34. line status register description.................................................................................. ................ 81 table 11-35. modem status register descriptiopn................................................................................ ........... 82 table 11-36. reset control of registers and pinout signals..................................................................... ....... 83 table 11-37. parallel port connector in different modes........................................................................ .......... 85 table 11-38. address map and bit map for spp and epp modes ................................................................... 86 table 11-39. bit map of the ecp registers ...................................................................................... ................ 89 table 11-40. ecp register definitions.......................................................................................... .................... 89 table 11-41. ecp mode descriptions ............................................................................................. .................. 89 table 11-42. ecp pin descriptions .............................................................................................. ..................... 90 table 11-43. extended control register (ecr) mode and description............................................................ 92 table 11-44. data register read/write controls ................................................................................. ........ 96
vii table 11-45. status register................................................................................................... .......................... 97 table 11-46. list of cir registers ............................................................................................. ....................... 99 table 11-47. modulation carrier frequency...................................................................................... .............. 104 table 11-48. receiver demodulation low frequency (hcfs = 0)................................................................. 105 table 11-49. receiver demodulation high frequency (hcfs = 1)................................................................ 106 figures figure 7-1. IT8673F special applications circuitry for intel piix4 ............................................................. ....... 11 figure 10-1. configuration sequence flow chart ................................................................................. ............ 14 figure 11-1. keyboard and mouse interface...................................................................................... ............... 96 figure 11-2. cir block diagram................................................................................................. ....................... 98
IT8673F preliminary v0.5 advanced input/output (advanced i/o) specifications subject to change without notice itpm-pn-200211 joseph, april 8, 2002 1 1. features pc98/99, acpi & landesk compliant ? isa plug and play register set compatible ? acpi v. 1.0 and landesk 3.1 compliant ? supports eight logical devices ? 16-bit address decoding ? three selectable dma channels ? pc98/99 i/o solution ? supports irq sharing fan controller ? provides fan on/off and speed control ? up to 3 programmable pulse width modulation (pwm) fan control outputs ? each pwm output supports 128 steps of pwm modes ? up to 3 fan tachometer inputs 2 serial ports ? supports two standard 16c550 uarts ? uart2 also supports irda 1.0 (sir) and askir infrared protocols ? supports midi baud rate ieee 1284 parallel port ? standard mode?bi-directional spp ? enhanced mode?epp v. 1.7 and epp v. 1.9 compliant ? high speed mode?ecp, ieee 1284 compliant ? backdrive current reduction ? printer power-on damage reduction floppy disk controller ? enhanced digital data separator ? drives a and b can be logically swapped via registers ? 3-mode drive supported ? supports automatic write protection via software ? supports two 360k/720k/1.2m/1.44m/2.88m floppy disk drives keyboard controller ? 8042 compatible ? 2kb programmable rom ? 256-byte data ram ? gatea20 and keyboard reset output ? supports keylock function (thru gpio) ? supports ps/2 mouse ? supports any key, or 2-5 sequential keys, or 1-3 simultaneous keys keyboard power-on feature ? supports mouse double-click and/or mouse move power on event consumer remote control (tv remote) ir 8 general purpose i/o pins ? input mode supports either switch de-bounce ? output mode supports 2 sets of programmable led blinking periods chasis open detection support serial irq support ite innovative automatic power-failure resume & power button de-bounce vbat & vcch support single 24 mhz or 48 mhz clock input single +5v power supply 128-pin qfp
IT8673F 2 2. general description the IT8673F is an isa-based highly integrated i/o device. the IT8673F provides all the functions required by legacy super i/o and fan controller functionalities. the IT8673F meets the ?microsoft ? pc98/99 system design guide? requirements and is acpi and landesk compliant. the IT8673F has integrated eight logical devices, featuring an fan controller. the fan speed controller is responsible to control three fan speeds through three 128 steps of pulse width modulation (pwm) output pins and to monitor three fans? tachometer inputs. other features include a high-performance 2.88mb floppy disk controller with digital data separator, which is able to support two 360k/720k/1.2m/1.44m/2.88m floppy disk drives. one multi-mode high-performance parallel port features the bi-directional standard parallel port (spp), the enhanced parallel port (epp, v.1.7 and v.1.9 are supported), and the ieee1284 compliant extended capabilities port (ecp). two 16c550 standard compatible enhanced uarts perform asynchronous communication with enhanced wireless irda 1.0 or askir protocols. one consumer ir controller supports multiple remote control ir protocols. the i/o device also has an integrated 8042 compatible keyboard controller with 2kb of programmable rom for customer application. these eight logical devices can be individually enabled or disabled via software configuration registers. the IT8673F utilizes power-saving circuitry to reduce power consumption and once a logical device is disabled the inputs are gated, the outputs are tri-state and the input clock is disabled. the IT8673F requires just a single 24/48 mhz clock input and operates with only single +5v power supply. the IT8673F is available in 128-pin qfp (quad flat package).
IT8673F 3 3. block diagram isa interface plug-and-play address central interface bus 16c550 uart1 control 16c550 uart2 + ir floppy disk controller keyboard controller general purpose i/o fan controller i/o ports mouse interface pwm signals to fets for fans floppy drive interface serial port 2 interface serial port 1 interface ir interface serial interrupt clock gen. 24/48 mhz osc. data keyboard interface ieee1284 parallel port parallel port interface consumer ir cir i/f
IT8673F 4 4. pinout table pin signal pin signal pin signal pin signal 1 nc 33 iochrdy 65 fan_ctl1 97 vbat 2 nc 34 sirq 66 gp10 98 copen# 3 nc 35 vcc 67 vcc 99 vcch 4 gnd 36 pciclk 68 gp17 100 slct 5 densel# 37 ior# 69 gp16 101 pe 6 motea# 38 iow# 70 gp15 102 busy 7 drvb# 39 sd0 71 gp14 103 ack# 8 drva# 40 sd1 72 fan_ctl2/gp13 104 gnd 9 moteb# 41 sd2 73 fan_tac2/gp12 105 pd7 10 gnd 42 sd3 74 drq1 106 pd6 11 dir# 43 gnd 75 drq2 107 pd5 12 step# 44 sd4 76 drq3 108 pd4 13 wdata# 45 sd5 77 gnd 109 pd3 14 wgate# 46 sd6 78 clkin 110 pd2 15 side1# 47 sd7 79 kdat 111 pd1 16 index# 48 sin1 80 kclk 112 pd0 17 tk00# 49 sout1 81 mdat 113 slin# 18 wpt# 50 dsr1# 82 mclk 114 init# 19 rdata# 51 rts1#/pin95sel 83 krst# 115 err# 20 dskchg# 52 cts1# 84 irrx 116 afd# 21 sa0 53 dtr1#/pin96sel 85 irtx 117 stb# 22 sa1 54 ri1# 86 ga20 118 aen 23 sa2 55 dcd1# 87 dack1# 119 reset 24 sa3 56 ri2# 88 dack2# 120 tc 25 sa4 57 dcd2# 89 dack3# 121 vcc 26 sa5 58 sin2 90 pson/gp11 122 nc 27 sa6 59 sout2 91 sa12 123 nc 28 sa7 60 dsr2# 92 sa13 124 nc 29 sa8 61 rts2#/kbc_irom 93 pwron#/pme# 125 nc 30 sa9 62 cts2# 94 panswh# 126 nc 31 sa10 63 dtr2#/kbcen 95 sa14/fan_tac3 127 nc 32 sa11 64 fan_tac1 96 sa15/fan_ctl3 128 nc
IT8673F 5 5. pin configuration densel# motea# drvb# drva# moteb# gnd dir# step# wgate# side1# index# tk00# wpt# dskchg# rdata# wdata# sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa9 sa10 sa11 iochrdy sirq pciclk vcc sa8 ior# iow# sd0 sd1 sd2 sd3 gnd sd4 sd5 sd6 sd7 sin1 sout1 dsr1# rts1#/pin95sel cts1# dtr1#/pin96sel ri1# dcd1# ri2# dcd2# sin2 sout2 dsr2# rts2#/kbc_irom cts2# dtr2#/kbcen nc nc nc gnd busy pe slct vcch copen# panswh# vbat pwron#/pme# sa13 sa12 pson/gp11 dack3# dack2# dack1# ga20 irtx fna_ctl2/gp13 irrx krst# mclk gp14 mdat kclk kdat clkin gnd drq3 gp15 drq2 drq1 fan_tac2/gp12 gp17 vcc gp10 fan_ctl1 gp16 ack# gnd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 slin# init# err# afd# stb# aen reset tc vcc nc nc nc nc nc nc nc fan_tac1 sa15/fan_ctl3 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 31 32 33 34 35 36 37 38 59 60 61 62 63 64 104 105 106 107 108 103 72 71 70 69 68 67 66 65 IT8673F 128-qfp sa14/fan_tac3 top view
IT8673F 6 6. IT8673F pin descriptions table 6-1. signal names (by pin numbers in alphabetical order) pin(s) no. signal i/o power description supplies 35, 67, 121 vcc pwr - +5v digital power supply. 99 vcch pwr - +5v vcc help supply. 97 vbat pwr - +3.3v battery supply. 4,10,43, 77, 104 gndd gnd - digital ground. isa bus interface signals 21-32 sa[0:11] di vcc isa address 0 - 11. input signals used to determine which internal register is accessed. sa0-sa11 are ignored during a dma access. 96 sa15/ fan_ctl3 di/ dod8 vcch isa address 15 / fan control output 3. ? the default function of this pin is isa address 15. ? the second function of this pin is the fan control output 3. ? the function of this pin is decid ed by the power-on strapping of dtr1#. 95 sa14/ fan_tac3 di/di vcch isa address 14 / fan tachometer input 3. ? the default function of this pin is isa address 14. ? the second function of this pin is the fan tachometer input 3. (0 to +5v amplitude fan tachometer input). ? the function of this pin is decid ed by the power-on strapping of rts1#. 92-91 sa[13:12] di vcch isa address 13 - 12. input signals used to determine which internal register is accessed. sa13-sa12 are ignored during a dma access. 39 - 42, 44 - 47 sd[0:7] dio24 vcc isa data 0 - 7. 8-bit bi-directional data lines used to transfer data between IT8673F and the cpu or dma controller. sd0 is the lsb and sd7 is the msb. 118 aen di vcc address enable . aen is used to disable the internal address decoder when it is high. this pin is always ignored during dma accesses. 74 - 76 drq[1:3] do8 vcc dma request 1 - 3. active high outputs to signal the dma controller that a data transfer from IT8673F is required. 87 ? 89 dack[1:3]# di vcch dma acknowledge 1 - 3 #. active low inputs to acknowledge the corresponding dma requests and enable the rd or wr signals during a dma access cycle. 36 pciclk di vcc pci clock . the pci clock input. 34 sirq dio24 vcc serial interrupt . 119 reset di vcc reset . a high level on this input resets IT8673F. this signal asynchronously terminates any activity and places the device in the disable state. 37 ior# di vcc i/o read # . active low input asserted by the cpu or dma controller to read data or status information from IT8673F. 120 tc di vcc terminal count . this input is asserted by the dma controller to indicate the end of a dma transfer. the signal is only effective during a dma access cycle. 38 iow# di vcc i/o write #. active low input asserted by the cpu or dma controller to write data or control information to IT8673F. 33 iochrdy dod24 vcc i/o channel ready. pulled low to extend the read/write command under the epp mode.
IT8673F 7 pin(s) no. signal i/o power description fan speed controller signals 65 fan_ctl1 dod8 vcc fan control output 1. (pwm output signal to fan ?s fet.) 72 fan_ctl2/ gp13 dod8/ diod8 vcc fan control output 2 / general purpose i/o 13. ? the default function of this pin is fan control output 2 (pwm output signal to fan ?s fet). ? the second function of this pin is the gp13. ? the function configuration of this pin is decided by the gpio configuration registers. 64 fan_tac1 di vcc fan tachometer input 1. (0 to +5v amplitude fan tachometer input) 73 fan_tac2/ gp12 di/ diod8 vcc fan tachometer input 2 / general purpose i/o 12. ? the default function of this pin is fan tachometer input 2. (0 to +5v amplitude fan tachometer input) ? the second function of this pin is the gp12. ? the function configuration of this pin is decided by the gpio configuration registers. serial port 1 signals 52 cts1# di vcc clear to send 1 #. when low, indicates that the modem or data set is ready to accept data. the cts# signal is a modem status input whose condition can be tested by reading the msr register. 55 dcd1# di vcc data carrier detect 1 #. when low, indicates that the modem or data set has detected a carrier. the dcd# signal is a modem status input whose condition can be tested by reading the msr register . 50 dsr1# di vcc data set ready 1 #. when low, indicates that the modem or data set is ready to establish a communications link. the dsr# signal is a modem status input whose condition can be tested by reading the msr register. 53 dtr1#/ pin96sel do8/di vcc data terminal ready 1 # / pin 96 multiplex select . ? the default function of this pin is data terminal ready 1 #. the dtr# signal is used to indicate to the modem or data set that the device is ready to exchange data. dtr# is activated by setting the appropriate bit in the mcr register to 1. after a master reset operation or during loop mode, dtr# is set to its inactive state. ? the second function of this pin is the power-on strapping of pin 96 multiplex select. when high, the pin 96 is selected as sa15. this pin is weak pull-up internally. 54 ri1# di vcc ring indicator 1 #. when low, indicates that a telephone ring signal has been received by the modem. the ri# signal is a modem status input whose condition can be tested by reading the msr register. 51 rts1#/ pin95sel do8/di vcc request to send 1 # / pin 95 multiplex select. ? the default function of this pin is request to send 1 #. when low, this output indicates to the modem or data set that the device is ready to send data. rts# is activated by setting the appropriate bit in the mcr register to 1. after a master reset operation or during loop mode, rts# is set to its inactive state. ? the second function of this pin is the power-on strapping of pin 95 multiplex select. when high, the pin 95 is selected as sa14. this pin is weak pull-up internally. 48 sin1 di vcc serial data in 1. this input receives serial data from the communications link.
IT8673F 8 pin(s) no. signal i/o power description 49 sout1 do8 vcc ? serial data out 1. this output sends serial data to the communications link. this signal is set to a marking state (logic 1) after a master reset operation or when the device is in one of the infrared communications modes. serial port 2 signals 62 cts2# di vcc clear to send 2 #. when low, indicates that the modem or data set is ready to accept data. the cts# signal is a modem status input whose condition can be tested by reading the msr register. 57 dcd2# di vcc data carrier detect 2 # . when low, indicates that the modem or data set has detected a carrier. the dcd# signal is a modem status input whose condition can be tested by reading the msr register. 60 dsr2# di vcc data set ready 2 #. when low, indicates that the modem or data set is ready to establish a communications link. the dsr# signal is a modem status input whose condition can be tested by reading the msr register. 63 dtr2#/ kbcen do8/di vcc data terminal ready 2 # / kbc enable. ? the default function of this pin is data terminal ready 2 #. dtr# is used to indicate to the modem or data set that the device is ready to exchange data. dtr# is activated by setting the appropriate bit in the mcr register to 1. after a master reset operation or during loop mode, dtr# is set to its inactive state. ? the second function of this pin is the power-on strapping of kbc (ldn 4) enable. this pin is weak pull-up internally. 56 ri2# di vcc ring indicator 2 #. when low, indicates that a telephone ring signal has been received by the modem. the ri# signal is a modem status input whose condition can be tested by reading the msr register. 61 rts2#/ kbc_irom do8/di vcc request to send 2 # / kbc internal rom selected ? the default function of this pin is request to send 2 #. when low, this output indicates to the modem or data set that the device is ready to send data. rts# is activated by setting the appropriate bit in the mcr register to 1. after a master reset operation or during loop mode, rts# is set to its inactive state. ? the second function of this pin is the power-on strapping of kbc intrusion rom select. when high (default), the internal rom is selected. when low, the external rom is selected. this pin is weak pull-up internally. 58 sin2 di vcc serial data in 2. this input receives serial data from the communications link. 59 sout2 do8 vcc serial data out 2. this output sends serial data to the communications link. this signal is set to a marking state (logic 1) after a master reset operation or when the device is in one of the infrared communications modes. parallel port signals 100 slct di vcc printer select. this signal goes high when the line printer has been selected. 101 pe di vcc printer paper end. this signal is set high by the printer when it runs out of paper. 102 busy di vcc printer busy. this signal goes high when the line printer has a local operation in progress and cannot accept data. 103 ack# di vcc printer acknowledge #. this signal goes low to indicate that the printer has already received a character and is ready to accept another.
IT8673F 9 pin(s) no. signal i/o power description 112 - 105 pd[0:7] dio24 vcc parallel port data bus 0-7. this bus provides a byte-wide input or output to the system. the eight lines are held in a high impedance state when the port is deselected. 113 slin# dio24 vcc printer select input #. when low, the printer is selected. this signal is derived from the complement of bit 3 of the printer control register. 114 init# dio24 vcc printer initialize #, active low. this signal is derived from bit 2 of the printer control register, and is us ed to initialize the printer. 115 err# di vcc printer error #, when active low it indicates that the printer has encountered an error. the error message can be read from bit 3 of the printer status register. 116 afd# dio24 vcc printer autolline feed #, active low. this signal is derived from the complement of bit 1 of the printer control register, and is used to advance one line after each line is printed. 117 stb# dio24 vcc printer strobe #, active low. this signal is the complement of bit 0 of the printer control register, and is used to strobe the printing data into the printer. floppy disk controller signals 5 densel# do40 vcc density select #. densel# is high for high data rates (500kbps, 1mbps). densel# is low for low data rates (250kbps, 300kbps) 6 motea# do40 vcc fdd motor a enable #. active low. 7 drvb# do40 vcc fdd drive b enable # . active low. 8 drva# do40 vcc fdd drive a enable #. active low. 9 moteb# do40 vcc fdd motor b enable # . active low. 11 dir# do40 vcc fdc head direction #. step in when low, step out when high during a seek operation. 12 step# do40 vcc fdc step pulse #. active low. 13 wdata# do40 vcc fdc write serial data to the drive #. active low. 14 wgate# do40 vcc fdc write gate enable #. active low. 15 side1# do40 vcc floppy disk side 1 select #. active low. 16 index# di vcc fdc index #. active low. indicates the beginning of a disk track. 17 tk00# di vcc floppy disk track 0 #. active low. indicates that the head of the selected drive is on track 0. 18 wpt# di vcc fdd write protect #. active low. indicates that the disk of the selected drive is write-protected. 19 rdata# di vcc fdc read disk data #. active low, serial data input from fdd 20 dskchg# di vcc floppy disk change #. active low. this is an input pin that senses whether the drive door has been opened or a diskette has been changed. keyboard controller signals 79 kdat diod16 vcch keyboard data. 80 kclk diod16 vcch keyboard clock. 81 mdat diod16 vcch ps/2 mouse data. 82 mclk diod16 vcch ps/2 mouse clock. 83 krst# dod8 vcch keyboard reset #. 86 ga20 dod8 vcch gate address 20.
IT8673F 10 pin(s) no. signal i/o power description infrared controller signals 85 irtx do16 vcch infrared data transmit. infrared data transmit. 84 irrx di vcch infrared data receive. infrared data receive low. miscellaneous signals 78 clkin di vcch 24 mhz or 48 mhz clock input. 66 gp10 diod8 vcc general purpose i/o 10 68 ? 71 gp[17:14] diod8 vcc general purpose i/o 17 - 14 98 copen# dod8 vcch or vbat case open detection #. the case open input is connected to a low power cmos flip-flop, which is especially designed to support the case open state by the battery during power loss state. 93 pwron#/ pme# dod8/ dod8 vcch power on switch output #/ power management event #. ? the first function of this pin is the main power on-off switch output # (bug fix for piix40). ? the second function of this pin is the power management event #. it supports the pci pme# interface. this signal allows the peripheral to request the system to wake up from d3 (cold) state. this pin is backed by vtr. ? the function configuration of this pin is decided by the software configuration registers. 94 panswh# di vcch panel switch input #. main power on-off switch input. (bug fix for piix4 ) 90 pson/gp11 dod8/ diod8 vcch power supply on output / general purpose i/o 11. ? the default function of this pin is main power supply on output. ( bug fix for piix4 ) ? the second function of this pin is the gp11. ? the function configuration of th is pin is decided by the gpio configuration registers. 1 ? 3, 133 ? 128 nc -- vcc ? no connection. io cell: do8: 8ma digital output buffer do16: 16ma digital output buffer do40: 48ma digital output buffer dod8: 8ma digital open-drain output buffer dod24: 24ma digital open-drain output buffer dio24: 24ma digital input/output buffer diod8: 8ma digital open-drain input/output buffer diod16: 16ma digital open-drain input/output buffer di: digital input
IT8673F 11 7. special pin routings psb - power supply bypass the psb will be internally routed to pson pin. IT8673F panswh# (94) intel piix4 pwron# (93) pson(90) pwbtn# susc# vcch system on-off button atx power supply pson# vcch figure 7-1. IT8673F special applications circuitry for intel piix4
IT8673F 12 8. list of gpio pins table 8-1. general purpose i/o pin(s) no. signal description 66 gp10 general purpose i/o 10. 90 pson/gp11 power supply on out put / general purpose i/o 11. 73 fan_tac2/gp12 fan tachometer input 2 / general purpose i/o 12. 72 fan_ctl2/gp13 fan control output 2 / general purpose i/o 13. 71 gp14 general purpose i/o 14. 70 gp15 general purpose i/o 15. 69 gp16 general purpose i/o 16. 68 gp17 general purpose i/o 17.
IT8673F 13 9. power on strapping options table 9-1. power on strapping pin no. signal value description 1 the function of the pin 95 is selected sa14. (default) 51 pin95sel 0 the function of the pin 95 is selected fan_tac3. 1 the function of the pin 96 is selected sa15. (default) 53 pin96sel 0 the function of the pin 96 is selected fan_ctl3. 1 kbc?s rom is built in. (default) 61 kbc_irom 0 kbc?s rom is external. this is used for custom code verification. a special application circuit is required. 1 kbc is enabled. (default) 63 kbcen 0 kbc is disabled.
IT8673F 14 10. configuration 10.1 configuring sequence description after the hardware reset or power-on reset, IT8673F enters the normal mode with all logical devices disabled except kbc. the initial state (enable bit) of this logical device (kbc) is determined by the state of pin 63 (dtr2# ) at the falling edge of the system reset during power-on reset. hardware reset wait for key string is the key port selected? wait for the next key i/o write to configuration address port? does the data match next key? does the data match last key? mb pnp mode are the four consecutive bytes correct? does the data match first key? save the i/o port as configuration port y y n y n n any other i/o transition cycle i/o write to 279h n y y n y n n figure 10-1. configuration sequence flow chart
IT8673F 15 there are three steps to completing configuration setup: (1) enter the mb pnp mode; (2) modify the data of configuration registers; (3) exit the mb pnp mode. without normal exiting, it may cause undesired results. (1) enter the mb pnp mode to enter the mb pnp mode, 36 special i/o write operations are to be performed during wait for key state. to insure the initial state of the key-check logic, it is first necessary to perform two write operations to the address port (279h) of the isa pnp. the entering key includes two steps. in the first step, four bytes are used to determine the i/o address and data port of configuration register. in the second step, 32 bytes are written to the address port determined by the first four bytes. all 36 bytes must be written properly and sequentially. the corresponding sequential data for the first four bytes are as follows: address port data port 86h, 80h, 55h, 55h; 3f0h 3f1h or 86h, 80h, 55h, aah; 3bdh 3bfh or 86h, 80h, aah, 55h; 370h 371h the sequential data for the other 32 bytes (same as the initial key of isa pnp, but written to different i/o ports) are listed below in hexadecimal numeration: 6a, b5, da, ed, f6, fb, 7d, be, df, 6f, 37, 1b, 0d, 86, c3, 61, b0, 58, 2c, 16, 8b, 45, a2, d1, e8, 74, 3a, 9d, ce, e7, 73, 39, (2) modify the data of the registers all configuration registers can be accessed after entering the mb pnp mode. before accessing a selected register, the content of index 07h must be changed to the ldn to which the register belongs. (3) exit the mb pnp mode set bit 1 of the configure control register (index 02h) to ?1? to exit the mb pnp mode.
IT8673F 16 10.2 description of the configuration registers all the registers except apc/pme# registers will be reset to the default state when reset is activated. table 10-1. global configuration registers ldn index r/w reset configuration register or action all 02h w na configure control all 07h r/w na logical device number (ldn) all 20h r 86h chip id byte 1 all 21h r 73h chip id byte 2 all 22h r 01h chip version all 23h r/w 00h clock selection register all 24h r/w 00h software suspend 07h *1 25h r/w 00h gpio multi-function pin selection register 07h *1 26h r/w 00h reserved 07h *1 27h r/w 00h reserved 07h *1 28h r/w 00h reserved 07h *1 29h r/w 00h reserved f4h *1 2eh r/w 00h test 1 register f4h *1 2fh r/w 00h test 2 register table 10-2. fdc configuration registers ldn index r/w reset configuration register or action 00h 30h r/w 00h fdc activate 00h 60h r/w 03h fdc base address msb register 00h 61h r/w f0h fdc base address lsb register 00h 70h r/w 06h fdc interrupt level select 00h 74h r/w 02h fdc dma channel select 00h f0h r/w 00h fdc special configuration register table 10-3. serial port 1 configuration registers ldn index r/w reset configuration register or action 01h 30h r/w 00h serial port 1 activate 01h 60h r/w 03h serial port 1 base address msb register 01h 61h r/w f8h serial port 1 base address lsb register 01h 70h r/w 04h serial port 1 interrupt level select 01h f0h r/w 00h serial port 1 special configuration register
IT8673F 17 table 10-4. serial port 2 configuration registers ldn index r/w reset configuration register or action 02h 30h r/w 00h serial port 2 activate 02h 60h r/w 02h serial port 2 base address msb register 02h 61h r/w f8h serial port 2 base address lsb register 02h 62h r/w 03h consumer ir base address msb register 02h 63h r/w 00h consumer ir base address lsb register 02h 70h r/w 03h serial port 2 interrupt level select 02h 72h r/w 00h consumer ir interrupt level select 02h f0h r/w 00h serial port 2 special configuration register 1 02h f1h r/w 40h serial port 2 special configuration register 2 table 10-5. parallel port configuration registers ldn index r/w reset configuration register or action 03h 30h r/w 00h parallel port activate 03h 60h r/w 03h parallel port primary base address msb register 03h 61h r/w 78h parallel port primary base address lsb register 03h 62h r/w 07h parallel port sec ondary base address msb register 03h 63h r/w 78h parallel port secondary base address lsb register 03h 70h r/w 07h parallel port interrupt level select 03h 74h r/w 03h parallel port dma channel select *2 03h f0h r/w 03h *3 parallel port special configuration register table 10-6. fan controller configuration registers ldn index r/w reset configuration register or action 04h 30h r/w 00h fan controller activate 04h 60h r/w 00h fan controller base address msb register 04h 61h r/w 80h fan controller base address lsb register 04h 62h r/w 02h pme# direct access base address msb register 04h 63h r/w 00h pme# direct access base address lsb register 04h 70h r/w 09h fan controller interrupt level select 04h f0h r/w 00h apc/pme# event enable register 04h f1h r/w 00h apc/pme# status register 04h f2h r/w 00h apc/pme# control register 1 04h f3h r/w 00h fan controller special configuration register 04h f4h r-r/w 00h apc/pme# control register 2 04h f5h r/w apc/pme# special code index register 04h f6h r/w apc/pme# special code data register
IT8673F 18 table 10-7. kbc(keyboard) configuration registers ldn index r/w reset configuration register or action 05h 30h r/w *4 kbc activate 05h 60h r/w 00h kbc data base address msb register 05h 61h r/w 60h kbc data base address lsb register 05h 62h r/w 00h kbc command base address msb register 05h 63h r/w 64h kbc command base address lsb register 05h 70h r/w 01h kbc interrupt level select 05h 71h r-r/w 02h kbc interrupt type *5 05h f0h r/w 00h kbc special configuration register table 10-8. kbc(mouse) configuration registers ldn index r/w reset configuration register or action 06h 30h r/w 00h kbc (mouse) activate 06h 70h r/w 0ch kbc (mouse) interrupt level select 06h 71h r-r/w 02h kbc (mouse) interrupt type *5 06h f0h r/w 00h kbc (mouse) special configuration register table 10-9. gpio configuration registers ldn index r/w reset configuration register or action 07h 60h r/w 00h cs0 base address msb register 07h 61h r/w 00h cs0 base address lsb register 07h 62h r/w 00h cs1 base address msb register 07h 63h r/w 00h cs1 base address lsb register 07h 64h r/w 00h cs2 base address msb register 07h 65h r/w 00h cs2 base address lsb register 07h 66h r/w 00h simple i/o base address msb register 07h 67h r/w 00h simple i/o base address lsb register 07h 68h r/w 00h panel button de-bounce base address msb register 07h 69h r/w 00h panel button de-bounce base address lsb register 07h 70h r/w 00h gp irq steering 1 control register 07h 71h r/w 00h gp irq steering 1 pin mapping register 07h 72h r/w 00h gp irq steering 2 control register 07h 73h r/w 00h gp irq steering 2 pin mapping register 07h f0h r/w 00h gp set selection register 07h f1h r/w 00h csx pin mapping register 07h f2h r/w 00h csx control register 07h f3h r/w 00h gpio pin polarity register 07h f4h r/w 00h gpio pin internal pu ll-up enable register
IT8673F 19 table 10-9. gpio & alternate function configuration registers (cont?d) ldn index r/w reset configuration register or action 07h f5h r/w 00h simple i/o enable register 07h f6h r/w 00h simple i/o direction selection register 07h f7h r/w 00h panel button de-bounce enable register 07h f8h r/w 00h panel button de-bounce control register / gp led blinking 2 control register 07h f9h r/w 00h keyboard lock pin mapping register 07h fah r/w 00h gp led blinking 1 pin mapping register 07h fbh r/w 00h gp led blinking control & ring# pin mapping register 07h fch r/w 00h gp led blinking 2 pin mapping register 07h fdh r/w 00h reserved register 07h feh r/w 00h pci clkrun# pin mapping register 07h ffh r/w 00h smi# pin mapping register 07h e0h r/w 00h smi# control register 1 07h e1h r/w 00h smi# control register 2 07h e2h r 00h smi# status register 1 07h e3h r-r/w 00h smi# status register 2 notes: *1: all these registers can be read from all ldns. *2: when the ecp mode is not enabled, this register is read only as ?04h?, and cannot be written. *3: when bit 2 of the base address of parallel port is set to 1, the epp mode cannot be enabled. bit 0 of this register is always 0. *4: the initial value of the activate bit of kbc is determined by the latched state of dtr2# at the falling edge of the reset signal. *5: these registers are read only unless the write enable bit (index=f0h) is asserted.
IT8673F 20 10.2.1 logical device base address the base i/o range of logical devices shown below is located in the base i/o address range of each logical device. table 10-10. base address of logical devices logical devices address notes ldn=0 fdc base + (2-5) and +7 ldn=1 serial port 1 base + (0-7) ldn=2 serial port 2 base1 + (0-7) base2 + (0-7) com port cir ldn=3 parallel port base1 + (0-3) base1 + (0-7) base1 + (0-3) and base2 + (0-3) base1 + (0-7) and base2 + (0-3) spp spp+epp spp+ecp spp+epp+ecp ldn=4 fan controller base1 + (0-7) base2 + (0-3) fan controller (fan) pme# ldn=5 kbc base1 + base2 kbc
IT8673F 21 10.3 global configuration registers (ldn: all) 10.3.1 configure control (index=02h) this register is write only . its values are not sticky; that is to say, a hardware reset will automatically clear the bits, and does not require the software to clear them. bit description 7-2 reserved 1 returns to the ?wait for key? state. this bit is used when configuration sequence is completed. 0 resets all logical devices and restores conf iguration registers to their power-on states. 10.3.2 logical device number (ldn, index=07h) this register is used to select the current logical devices. by reading from or writing to the configuration of i/o, interrupt, dma and other special functions, all registers of the logical devices can be accessed. in addition, activate command is only effective for the selected logical devices. this register is read/write . 10.3.3 chip id byte 1 (index=20h, default=86h) this register is the chip id byte 1 and is read only . bits [7:0]=86h when read. 10.3.4 chip id byte 2 (index=21h, default=73h) this register is the chip id byte 2 and for read only . bits [7:0]=73h when read. 10.3.5 chip version (index=22h, default=01h) this register is the chip version and for read only . 10.3.6 clock selection register (index=23h, default=00h) bit description 7-1 reserved 0 clkin frequency. 1: 48 mhz. 0: 24 mhz. 10.3.7 software suspend (index=24h, default=00h, mb pnp) this register is the software suspend register. when bit 0 is set, IT8673F enters the ?software suspend? state. all the devices, except kbc, remain inactive until this bit is cleared or when the wake-up event occurs. the wake-up event occurs at any transition on signals ri1# (pin 54) and rl2# (pin 56).
IT8673F 22 10.3.8 gpio multi-function pin selection register (index=25h, default=00h) if the enabled bits are not set, the multi-function pins will perform the original functions. on the other hand, if they are set, they will perform the gpio functions. this register can be read from any ldn, but can only be written if ldn=07h. bit description 7 selects the gpio function of general purpose i/o 17 (gp17) of pin 68. 6 selects the gpio function of general purpose i/o 16 (gp16) of pin 69. 5 selects the gpio function of general purpose i/o 15 (gp15) of pin 70. 4 selects the gpio function of general purpose i/o 14 of pin 71. 3 performs the function selection of fan_ctl2 or gp 13 of pin 72. 1: selects the function of general purpose i/o 13 (gp13). 0: selects the function of fa n control output 2 (fan_ctl2). 2 performs the function selection of fan_tac2 or gp 12 of pin 73. 1: selects the function of general purpose i/o 12 (gp12). 0: selects the function of fan tachometer input 2 (fan_tac2). 1 performs the function selection of pson or gp 11 of pin 90. 1: selects the function of general purpose i/o 11 (gp11). 0: selects the function of power supply on output (pson). 0 selects the gpio function of general purpose i/o 10 (gp10) of pin 66. 10.3.9 reserved register (index=26h, default=00h) 10.3.10 reserved register (index=27h, default=00h) 10.3.11 reserved register (index=28h, default=00h) 10.3.12 reserved register (index=29h, default=00h) 10.3.13 test 1 register (index=2eh, default=00h) this register is the test 1 register and is reserved for ite. it should not be set. 10.3.14 test 2 register (index=2fh, default=00h) this register is the test 2 register and is reserved for ite. it should not be set. 10.4 fdc configuration registers (ldn=00h) 10.4.1 fdc activate (index=30h, default=00h) bit description 7-1 reserved 0 fdc enable. 1: enabled. 0: disabled.
IT8673F 23 10.4.2 fdc base address msb register (index=60h, default=03h) bit description 7-4 read only , with ?0h? for base address [15:12]. 3-0 mapped as base address [11:8]. 10.4.3 fdc base address lsb register (index=61h, default=f0h) bit description 7-3 read/write , mapped as base address[7:3]. 2-0 read only as ?000b?. 10.4.4 fdc interrupt level select (index=70h, default=06h) bit description 7-4 reserved with default ?0h?. 3-0 select the interrupt level note1 for fdc. 10.4.5 fdc dma channel select (index=74h, default=02h) bit description 7-3 reserved with default ?00h?. 2-0 select the dma channel note2 for fdc. 10.4.6 fdc special configuration register (index=f0h, default=00h) bit description 7-4 reserved with default ?00h?. 3 1 : irq sharing. 0 : normal irq. 2 1 : swap floppy drives a, b. 0 : normal. 1 1 : 3-mode. 0 : at mode. 0 1 : software write protect. 0 : normal. 10.5 serial port 1 configuration registers (ldn=01h) 10.5.1 serial port 1 activate (index=30h, default=00h) bit description 7-1 reserved 0 serial port 1 enabled. 1: enabled. 0: disabled.
IT8673F 24 10.5.2 serial port 1 base address msb register (index=60h, default=03h) bit description 7-4 read only as ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8]. 10.5.3 serial port 1 base address lsb register (index=61h, default=f8h) bit description 7-3 read/write , mapped as base address[7:3]. 2-0 read only as ?000b?. 10.5.4 serial port 1 interrupt level select (index=70h, default=04h) bit description 7-4 reserved with default ?0h?. 3-0 select the interrupt level note1 for serial port 1. 10.5.5 serial port 1 special configuration register (index=f0h, default=00h) bit description 7-3 reserved with default ?00h?. 2-1 clock source. 00: 24 mhz/13 (standard) 01: 24 mhz/12 (midi) 10: reserved 11: reserved 0 1 : irq sharing. 0 : normal. 10.6 serial port 2 configuration registers (ldn=02h) 10.6.1 serial port 2 activate (index=30h, default=00h) bit description 7-1 reserved 0 serial port 2 enable. 1: enabled. 0: disabled.
IT8673F 25 10.6.2 serial port 2 base address msb register (index=60h, default=02h) bit description 7-4 read only with ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8]. 10.6.3 serial port 2 base address lsb register (index=61h, default=f8h) bit description 7-3 read/write , mapped as base address[7:3]. 2-0 read only as ?000b?. 10.6.4 consumer ir base address msb register (index=62h, default=03h) bit description 7-4 read only with ?0h? for base address[15:12]. 3-0 read/write, mapped as base address[11:8]. 10.6.5 consumer ir base address lsb register (index=63h, default=00h) bit description 7-3 read/write , mapped as base address[7:3]. 2-0 read only as ?000b?. 10.6.6 serial port 2 interrupt level select (index=70h, default=03h) bit description 7-4 reserved with default ?0h?. 3-0 select the interrupt level note1 for serial port 2. 10.6.7 consumer ir interrupt level select (index=72h, default=00h) bit description 7-4 reserved with default ?0h.? 3-0 select the interrupt level note1 for serial port 2.
IT8673F 26 10.6.8 serial port 2 special configuration register 1 (index=f0h, default=00h) bit description 7-3 reserved with default ?00h.? 2-1 clock source. 00: 24 mhz/13 (standard) 01: 24 mhz/12 (midi) 10: reserved 11: reserved 0 1 : irq sharing. 0 : normal. 10.6.9 serial port 2 special configuration register 2 (index=f1h, default=40h) bit description 7 1: no transmission delay (40 bits) when the sir or askir is changed from rx mode to tx mode. 0: transmission delay (40 bits) when the sir or askir is changed from rx mode to tx mode. 6 1: no reception delay (40 bits) when the sir or askir is changed from tx mode to rx mode. 0: reception delay (40 bits) when the sir or askir is changed from tx mode to rx mode. 5 single mask mode: when set, the rx of uart is masked under tx transmission. 4 1 : half duplex. 0 : full duplex (default). 3 cir enable. 2-0 ir mode select 000: standard (default). 001: irda 1.0 (hp sir). 010 : askir. else : reserved. 10.7 parallel port configuration registers (ldn=03h) 10.7.1 parallel port activate (index=30h, default=00h) bit description 7-1 reserved 0 parallel port enabled. 1: enabled. 0: disabled. 10.7.2 parallel port primary base address msb register (index=60h, default=03h) bit description 7-4 read only as ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8].
IT8673F 27 10.7.3 parallel port primary base address lsb register (index=61h, default=78h) if bit 2 is set to 1, the epp mode is disabled automatically. bit description 7-2 read/write , mapped as base address[7:2]. 1-0 read only as ?00b?. 10.7.4 parallel port secondary base address msb register (index=62h, default=07h) bit description 7-4 read only as ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8]. 10.7.5 parallel port secondary base address lsb register (index=63h, default=78h) bit description 7-2 read/write , mapped as base address[7:2]. 1-0 read only as ?00b?. 10.7.6 parallel port interrupt level select (index =70h, default=07h) bit description 7-4 reserved with default ?0h?. 3-0 select the interrupt level note1 for parallel port. 10.7.7 parallel port dma channel select (index=74h, default=03h) bit description 7-3 reserved with default ?00h.? 2-0 select the dma channel note2 for parallel port. 10.7.8 parallel port special configuration register (index=f0h, default=03h) bit description 7-3 reserved 2 1 : irq sharing. 0 : normal. 1-0 parallel port mode 00 : standard parallel port mode (spp) 01 : epp mode 10 : ecp mode 11 : epp mode and ecp mode
IT8673F 28 if bit 1 is set, ecp mode is enabled. if bit 0 is set, epp mode is enabled. these two bits are independent. however, according to the epp spec., when parallel port primary base address bit 2 is set to 1, the epp mode cannot be enabled. 10.8 fan controller configuration registers (ldn=04h) 10.8.1 fan controller activate register (index=30h, default=00h) bit description 7-1 reserved 0 fan controller enabled. 1: enabled. 0: disabled. 10.8.2 fan controller base address msb register (index=60h, default=00h) bit description 7-4 read only as ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8]. 10.8.3 fan controller base address lsb register (index=61h, default=80h) bit description 7-3 read/write , mapped as base address[7:3]. 2-0 read only as ?000b?. 10.8.4 pme# direct access base address msb register (index=62h, default=02h) bit description 7-4 read only as ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8]. 10.8.5 pme# direct access base address lsb register (index=63h, default=00h) bit description 7-3 read/write , mapped as base address[7:3]. 2-0 read only as ?000b?. 10.8.6 fan controller interrupt level select (index=70h, default=09h) bit description 7-4 reserved with default ?0h?. 3-0 select the interrupt level note1 for fan controller.
IT8673F 29 10.8.7 apc/pme# event enable register (per) (index=f0h, default=00h) bit description 7 it is set to 1 when vcch is off. writing 1 to clear this bit. this bit is ineffective if a 0 is written to this bit. 6 reserved 5 ring# event enable. 1 : enabled. 0 : disabled. 4 ps/2 mouse event enable. 1 : enabled. 0 : disabled. 3 keyboard event enable. 1 : enabled. 0 : disabled. 2 ri2# event enable. 1 : enabled. 0 : disabled. 1 ri1# event enable. 1 : enabled. 0 : disabled. 0 reserved 10.8.8 apc/pme# status register (psr) (index=f1h, default=00h) bit description 7 it is set to 1 when vcc is on at last ac power failure and 0 when vcc is off. 6 reserved 5 ring# event detected. 4 ps/2 mouse event detected. 3 keyboard event detected. 2 ri2# event detected. 1 ri1# event detected. 0 reserved
IT8673F 30 10.8.9 apc/pme# control register 1 (pcr 1) (index=f2h, default=00h) bit description 7 per and psr normal run access enable. 6 reserved 5 this bit is restored automatically to the previous vcc state before power failure occurs. 4 disables all apc events after the powe r failure occurs, excluding panswh#. 3 keyboard event mode selection when vcc is on. 1 : determined by pcr 2. 0 : pulse falling edge on kclk. 2 mouse event when vcc is off. 1 : double click key. 0 : pulse falling edge on mclk. 1 mouse event when vcc is on. 1 : double click key. 0 : pulse falling edge on mclk. 0 ring# event mode selection. 1 : pulse train mode. 0 : pulse falling edge mode. 10.8.10 fan controller special configuration register (index=f3h, default=00h) bit description 7-1 reserved 0 1 : irq sharing. 0 : normal. 10.8.11 apc/pme# control register 2 (pcr 2) (index=f4h, default=00h) bit description 7 pin 93 function selection. 1: pme#. 0: apc pwron#. 6 reserved 5 pson state when vcch is switched from off to on under vcc off state. 4 masks panswh# power-on event. 3-2 key number of the keyboard power-up event. 00: 5 (key string mode), 3(stro ke keys at same time mode) 01: 4 (key string mode), 2(stroke keys at same time mode) 10: 3 (key string mode), 1(stro ke keys at same time mode) 11: 2 (key string mode), reserved (stroke keys at same time mode) 1-0 keyboard power-up event mode selection. 00: kclk falling edge 01: key string mode 10: stroke keys at same time mode 11: reserved
IT8673F 31 10.8.12 apc/pme# special code index register (index=f5h) bit description 7-6 reserved (should be ?00?) 5-0 indicate which identification key code or cir code register is to be read/written via 0xf6. 10.8.13 apc/pme# special code data register (index=f6h) there are 5 bytes for key string mode, and 3 bytes for stroke keys at same time mode. 10.9 kbc (keyboard) configuration registers (ldn=05h) 10.9.1 kbc (keyboard) activate (index=30h, default=01h or 00h) bit description 7-1 reserved 0 kbc(keyboard) enable. 1: enabled. 0: disabled. this is a read/write register. the default value depends on the state of the dtr2# when reset is activated. the default value is 1b for the high state of dtr2# when reset is activated. it is 0b for the low state of dtr2# when reset is activated. 10.9.2 kbc (keyboard) data base address msb register (index=60h, default=00h) bit description 7-4 read only as ?0h? for base address [15:12]. 3-0 read/write , mapped as base address [11:8]. 10.9.3 kbc (keyboard) data base address lsb register (index=61h, default=60h) bit description 7-0 read/write , mapped as base address[7:0]. 10.9.4 kbc (keyboard) command base address msb register (index=62h, default=00h) bit description 7-4 read only as ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8]. 10.9.5 kbc (keyboard) command base address lsb register (index=63h, default=64h) bit description 7-0 read/write , mapped as base address[7:0].
IT8673F 32 10.9.6 kbc (keyboard) interrupt level select (index=70h, default=01h) bit description 7-4 reserved with default ?0h?. 3-0 select the interrupt level note1 for kbc (keyboard). 10.9.7 kbc (keyboard) interrupt type (index=71h, default=02h) this register indicates the type of interrupt set for kbc (keyboard) and is read only as ?02h? when bit 1 of the kbc (keyboard) special configuration register is cleared. if set, this type of interrupt can be selected as level or edge trigger. bit description 7-2 reserved 1 1: high level. 0: low level. 0 1: level type. 0: edge type. 10.9.8 kbc (keyboard) special configuration register (index=f0h, default=00h) bit description 7 reserved 6 reserved 5 reserved 4 1: irq sharing. 0: normal. 3 1:kbc?s clock 8 mhz. 0:kbc?s clock 12 mhz. 2 1: key lock enabled. 0: key lock disabled. 1 1: type of interrupt of kbc (keyboard) can be changed. 0: type of interrupt of kbc (keyboard) is fixed. 0 1: enables the external access rom of 8042. 0: internal built-in rom is used. 10.10 kbc (mouse) configuration registers (ldn=06h) 10.10.1 kbc (mouse) activate (index=30h, default=00h) bit description 7-1 reserved 0 kbc (mouse) enable. 1: enabled. 0: disabled. 10.10.2 kbc (mouse) interrupt level select (index=70h, default=0ch) bit description 7-4 reserved with default ?0h?. 3-0 select the interrupt level note1 for kbc (mouse).
IT8673F 33 10.10.3 kbc (mouse) interrupt type (index=71h, default=02h) this register indicates the type of interrupt used for kbc (mouse) and is read only as ?02h? when bit 0 of the kbc (mouse) special configuration register is cleared. when bit 0 is set, the type of interrupt can be selected as level or edge trigger. bit description 7-2 reserved 1 1: high level. 0: low level. 0 1: level type. 0: edge type. 10.10.4 kbc (mouse) special configuration register (index=f0h, default=00h) bit description 7-2 reserved with default ?00h.? 1 1: irq sharing. 0: normal. 0 1: type of interrupt of kbc (mouse) can be changed. 0: type of interrupt of kbc (mouse) is fixed. 10.11 gpio configuration registers (ldn=07h) 10.11.1 cs0 base address msb register (index=60h, default=00h) bit description 7-4 read only as ?0h? for base address [15:12]. 3-0 read/write , mapped as base address [11:8]. 10.11.2 cs0 base address lsb register (index=61h, default=00h) bit description 7-0 read/write , mapped as base address[7:0]. 10.11.3 cs1 base address msb register (index=62h, default=00h) bit description 7-4 read only as ?0h? for base address [15:12]. 3-0 read/write , mapped as base address [11:8]. 10.11.4 cs1 base address lsb register (index=63h, default=00h) bit description 7-0 read/write , mapped as base address[7:0].
IT8673F 34 10.11.5 cs2 base address msb register (index=64h, default=00h) bit description 7-4 read only as ?0h? for base address [15:12]. 3-0 read/write , mapped as base address [11:8]. 10.11.6 cs2 base address lsb register (index=65h, default=00h) bit description 7-0 read/write , mapped as base address[7:0]. 10.11.7 simple i/o base address msb register (index=66h, default=00h) bit description 7-4 read only as ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8]. 10.11.8 simple i/o base address lsb register (index=67h, default=00h) bit description 7-0 read/write , mapped as base address[7:0]. 10.11.9 panel button de-bounce base address msb register (index=68h, default=00h) bit description 7-4 read only as ?0h? for base address[15:12]. 3-0 read/write , mapped as base address[11:8]. 10.11.10 panel button de-bounce base address lsb register (index=69h, default=00h) bit description 7-0 read/write , mapped as base address[7:0].
IT8673F 35 10.11.11 gp irq steering 1 control register (index=70h, default=00h) bit description 7-4 reserved 3-0 select the interrupt level note1 for gpio. 10.11.12 gp irq steering 1 pin mapping register (index=71h, default=00h) bit description 7 reserved 6 gp irq steering 1 irq sharing enable. 5-0 please see location mapping table note3 on page 40. 10.11.13 gp irq steering 2 control register (index=72h, default=00h) bit description 7-4 reserved 3-0 select the interrupt level note1 for gpio. 10.11.14 gp irq steering 2 pin mapping register (index=73h, default=00h) bit description 7 reserved 6 gp irq steering 1 irq sharing enabled. 5-0 please see location mapping table note3 on page 40. 10.11.15 gp set selection register (index=f0h, default=00h) this register is used to determine which set will be accessed by the later accessing of index f1h, f2h. if accessing f3h, f4h, f5h, f6h, and f7h, this register should be fixed at 00h. please refer to the location mapping table note3 on page 40. 10.11.16 csx pin mapping register (index=f1h, default=00h) this register is used to determine csx output pin mapping. before accessing this register, the gp set selection register must be determined first (00h for cs0, 01h for cs1 and 02h for cs2). bit description 7-6 reserved 5-0 please see location mapping table note3 on page 40.
IT8673F 36 10.11.17 csx control register (index=f2h, default=00h) before accessing this register, the gp set selection register must be determined first (00h for cs0, 01h for cs1 and 02h for cs2). bit description 7-6 reserved 3-2 base address alignment. 00 : single port 01 : 2 ports 10 : 4 ports 11 : 8 ports 1-0 chip select type. 00 : pure address decode 01 : address decode and ior command 10 : address decode and iow command 11 : address decode and (ior or iow command) 10.11.18 gpio pin polarity register (index=f3h, default=00h) this register is used to program the gp pin type as polarity inverting or non-inverting. before accessing this register, the gp set selection register must be fixed at 00h. bit description 7-0 for each bit 1: inverting. 0: non-inverting. 10.11.19 gpio pin internal pull-up enable register (index=f4h, default=00h) before accessing this register, the gp set selection register must be fixed at 00h. bit description 7-0 for each bit 1: enabled. 0: disabled. 10.11.20 simple i/o enable register (index=f5h, default=00h) this register is used to select the function as either the simple i/o or the alternate function. before accessing this register, the gp set selection register must be fixed at 00h. bit description 7-0 for each bit 1: simple i/o. 0: alternate function.
IT8673F 37 10.11.21 simple i/o direction selection register (index=f6h, default=00h) this register is used to determine the direction of the simple i/o. before accessing this register, the gp set selection register must be fixed at 00h. bit description 7-0 for each bit 1: input mode. 0: output mode. 10.11.22 panel button de-bounce enable register (index=f7h, default=00h) before accessing this register, the gp set selection register must be fixed at 00h. bit description 7-0 for each bit 1: enabled. 0: disabled. 10.11.23 panel button de-bounce control register/gp led blinking 2 control register (index=f8h, default=00h) bit description 7 gp led 2 short low pulse enable. 6-5 gp led 2 frequency control. 00: 4 hz. 01: 1 hz. 10: 1/4 hz. 11: 1/8 hz. 4 gp led 2 output low enable. 3 irq output type. 0: edge mode. 1: level mode. 2 irq output enable. 0: disabled. 1: enabled. 1-0 de-bounce time selection. 00: 8 ms (6 ms ignored, 8 ms pass) 01: 16 ms (12 ms ignored, 16 ms pass) 10: 32 ms (24 ms ignored, 21 ms pass) 11: 64 ms (48 ms ignored, 64 ms pass) 10.11.24 keyboard lock pin mapping register (index=f9h, default=00h) bit description 7-6 reserved 5-0 keyboard lock pin location. please see location mapping table note3 on page 40.
IT8673F 38 10.11.25 gp led blinking 1 pin mapping register (index=fah, default=00h) bit description 7-6 reserved 5-0 gp led blinking location. please see location mapping table note3 on page 40 . 10.11.26 gp led blinking control and ring# pin mapping register (index=fbh, default=00h) bit description 7 reserved 6-4 location of ring#. 000 : gpio10 010 : gpio11 (only this pin can work under vcch power) 011 : gpio12 100 : gpio13 101 : gpio14 110 : gpio15 001 : gpio16 111 : gpio17 3 gp led 1 short low pulse enable. 2-1 gp led 1 frequency control. 00: 4 hz 01: 1 hz 10: 1/4 hz 11: 1/8 hz 0 gp led 1 output low enabled. 10.11.27 gp led blinking 2 pin mapping register (index=fch, default=00h) bit description 7-6 reserved 5-0 gp led 2 pin location. please see location mapping table note3 on page 40 . 10.11.28 reserved register (index=fdh, default=00h) 10.11.29 pci clkrun# pin mapping register (index=feh, default=00h) bit description 7-6 reserved 5-0 pci clkrun# pin location. please see location mapping table note3 on page 40.
IT8673F 39 10.11.30 smi# pin mapping register (index=ffh, default=00h) bit description 7-6 reserved 5-0 smi# pin location. please see location mapping table note3 on page 40 . 10.11.31 smi# control register 1 (index=e0h, default=00h) bit description 7 enables the generation of an smi# due to gp irq steering 1?s irq (en_gpirq1). 6 enables the generation of an smi# due to kbc(ps/2 mouse)?s irq (en_mirq). 5 enables the generation of an smi# due to kbc(keyboard)?s irq (en_kirq). 4 enables the generation of an smi# due to fan controller?s irq (en_ecirq). 3 enables the generation of an smi# due to parallel port?s irq (en_pirq). 2 enables the generation of an smi# due to serial port 2?s irq (en_s2irq). 1 enables the generation of an smi# due to serial port 1?s irq (en_s1irq). 0 enables the generation of an smi# due to fdc?s irq (en_firq). 10.11.32 smi# control register 2 (index=e1h, default=00h) bit description 7 forces to clear all the smi# st atus register bits, non-sticky. 6 0: edge trigger. 1: level trigger. 5-2 reserved 1 enables the generation of an smi# due to apc switch button(en_btn). 0 enables the generation of an smi# due to gp irq steering 2?s irq (en_gpirq2). 10.11.33 smi# status register 1 (index=e2h, default=00h) this register is used to read the status of smi# inputs. bit description 7 gp irq steering 1?s irq. 6 kbc(ps/2 mouse)?s irq. 5 kbc(keyboard)?s irq. 4 fan controller?s irq. 3 parallel port?s irq. 2 serial port 2?s irq. 1 serial port 1?s irq. 0 fdc?s irq.
IT8673F 40 10.11.34 smi# status register 2 (index=e3h, default=00h) this register is used to read the status of smi# inputs. bit description 7-2 reserved 1 apc switch button. 0 gp irq steering 2?s irq. note1 : interrupt level mapping fh-dh: not valid ch : irq12 . . 3h : irq3 2h : not valid 1h : irq1 0h : no interrupt selected note2 : dma channel mapping 7h-5h : not valid 4h : no dma channel selected 3h : dma3 2h : dma2 1h : dma1 0h : not valid note3 : the location mapping location description 001 000 gpio10 (pin 66). 001 001 gpio11 (pin 90). powered by vcch. 001 010 gpio12 (pin 73). 001 011 gpio13 (pin 72). 001 100 gpio14 (pin 71). 001 101 gpio15 (pin 70). 001 110 gpio16 (pin 69). 001 111 gpio17 (pin 68). else reserved
IT8673F 41 11. functional description 11.1 general purpose i/o IT8673F provides flexible i/o control and special functions for the system designers through a set of general purpose i/o pins (gpio). some of gpio pins are multi-functional. the gpio functions will not be performed unless the related enable bits of the gpio multi-function pin selection register (index 25h of global configuration register) are set. gpio function includes the simple i/o function and alternate function, and the function selection is determined by simple i/o enable register (index=f5h). the simple i/o function includes a set of registers, which correspond to the gpio pins. the accessed i/o ports are programmable. base address is programmed on the gpio simple i/o base address lsb and msb registers (ldn=07h, index=66h and 67h). the alternate function provides several special functions for users, including three chip select strobes (cs0, cs1, cs2), smi# output routing, interrupt steering, panel button de-bounce, keyboard lock input routing, led blinking, pci clkrun# routing, and ring routing (sub-function of apc). all these functions can be programmed to all gpio pins, except the ring# function. the gp set selection register (index=f0h) is used to determine the set x of the some registers (index=f1h and f2h). before these registers can be programmed, this register (index=f0h) must be determined in first. IT8673F provides flexible control registers related to each of three chip select strobes. each chip select strobe can be programmed as 1, 2, 4 or 8 via consecutive i/o ports decoding. each chip select strobe can also be programmed to qualify with ior# or iow# strobe. there are four types of qualifying conditions: pure address decided, asserted on address matching and ior# asserted, asserted on address matching and iow# asserted, asserted on address matching and ior# or iow# asserted. the key lock function locks the keyboard to invalidate any key stroke. the programming method is to set bit 2 on the kbc (keyboard) special configuration register (index=f0h, ldn=05h). the keyboard lock pin mapping register (index=f9h) must also be programmed correctly. the interrupt steering function provides a useful feature for motherboard designers. through this mapping method, the interrupt of other on-board devices can be easily modified by programming the registers of index = 70h, 71h, 72h, and 73h. the blinking function provides a low frequency blink output. by connecting to some external components, it can be used to control a power led. there are several frequencies that can be selected. the pci clkrun# output is used to resume the pci clock in system power down mode, when the IT8673F devices (serial port 1, serial port 2, parallel port?) request to generate an interrupt through sirq protocol. all the devices will not be resumed unless the related enable bits in smi# control register 1 and 2 are set. the smi# is a non-maskable interrupt dedicated for transparent power management. it consists of different enable interrupts from each of the functional blocks in IT8673F. the interrupts are enabled onto the smi# output via the smi# control register 1 and smi# control register 2. the smi# status registers 1 and 2 are used to read the status of the smi input events. all the smi# status register bits can be cleared when the corresponding sources events become invalidated. these bits can also be cleared by writing 1 to bit 7 of smi# control register 2, whether the events of the corresponding sources are invalidated or not. the smi# can be programmed as pulse mode or level mode whenever an smi# event occurs. the logic equation of the smi# event is described below: smi# event = (en_firq and firq) or (en_s1irq and s1irq) or (en_s2irq and s2irq) or (en_pirq and pirq) or (en_kbc(keyboard) and kirq) or (en_kbc(mouse) and mirq) or (en_gpirq1 and gpirq1) or (en_gpirq2 or gpirq2).
IT8673F 42 11.2 advanced power supply control and pme# the circuit for advanced power supply control (apc) provides three power-up events, keyboard, mouse, and ring#. when any of these three events is true, pwron# will perform a low state until vcc is switched to on state. the three events include: 1. detection of ring# pulse or pulse train on the programmed ring# input pin(ldn=04h, index=fbh, bits 6-4). 2. detection of kclk edge or special pattern of kclk and kdat. the special pattern of kclk means pressing pre-set key string sequentially, and kdat means pressing pre-set keys simultaneously. 3. detection of mclk edge or special pattern of mclk and mdat. the special pattern of mclk and mdat means double clicking on any mouse buttons. the panswh# and pson are especially designed for piix4. panswh# serves as a main power switch input which is wire-and to the apc output pwron#. pson is the atx power control output, which is a power-failure gating circuit. the power-failure gating circuit is responsible for gating the susc# until panswh# becomes active when the vcch is switched from off to on. the power-failure gating circuit can be disabled by setting the apc/pme control register 2 (ldn=04h, index=f4h, bit 5). the gating circuit also provides an auto-restore function. when the bit 5 of pcr1 is set, the previous pson state will be restored when the vcch is switched from off to on. the ring# function is used to power on the system from modem, fax, etc. it can be programmed to detect a pulse train with pulse low. the mask pwron# activation bit (bit 4 of pcr 1) is used to mask all power-up events except switch on event when the vcch state is just switched from fail to off. in other words, when this bit is set and the power state is switched from fail to off, the only validated function is panswh#. the pcr2 register is responsible for determining the keyboard power up events and apc conditions. bit 7 of pcr2 is used to select the function of pin 93 (apc power up events or pci pme# output). bit 4 is used to mask the panswh# power-on event. to enable this bit, the keyboard power-up event should be enabled and set by (1) pressing pre-set key string sequentially or (2) stroking pre-set keys simultaneously. the apc/pme# special code index and data registers are used to specify the special key codes in the special power-up events of (1) pressing pre-set key string sequentially or (2) stroking pre-set keys simultaneously. when bit 7 of pcr2 is set to 1, pme# function is selected. there are two differences. when any one of the three power-up events is true, the output of pin 115 goes low until the corresponding status bit is written to ?1?. pme# function is validated in both vcc on and off states. all apc registers (index=f0h, f2h, f4h, f5h and f6h) are powered by back-up power (vbat) when vcch is off. 11.3 fan controller the fan controller, built in the IT8673F, include three fan tachometers, and three sets of advanced fan controllers. fan tachometer inputs are digital inputs with an acceptable input range of 0v to 5v, and are responsible for measuring the fan?s tachometer pulse periods. fan_tac1 and fan_tac2 are included with programmable divisors, and can be used to measure different fan speed ranges. fan_tac3 is included with fixed divisor, and can only be used in default range.
IT8673F 43 11.3.1 interfaces isa bus: the fan controller of IT8673F decodes four addresses on the isa bus. table 11-1. address map on the isa bus register or port address address register of the fan controller base+05h data register of the fan controller base+06h note 1. the base address is determined by the logical devi ce configuration registers of fan controller (ldn=04h, registers index= 60h, 61h). to access an fan controller?s register, the address of the register is written to the address port (base+05h). read or write data from or to that register via data port (base+06h). 11.3.2 registers 11.3.2.1 address port (base+05h, default=00h) bit description 7 outstanding; read only this bit is set when a data write is performed to address port via the isa bus or when a serial bus transaction is in progress. this bit can be cleared when the serial bus transaction is completed, or when a data write/read is performed to/from data port. 6-0 index: internal address of ram and registers.
IT8673F 44 44 table 11-2. fan controller registers index register default description 28h-2ah fan_tac1-3 reading - fan tachometer 1-3 reading register ; the counts number of the internal clock per resolution 3bh-3dh fan_tac1-3 limit - fan tach ometer 1-3 count limit register 40h configuration 08h 41h interrupt status 1 00h auto increment to the index of interrupt status 2 42h interrupt status 2 00h 43h smi# mask 1 00h auto increment to the index of smi# mask 2 44h smi# mask 2 00h 45h interrupt mask 1 00h auto increment to the index of interrupt mask 2 46h interrupt mask 2 0xh 47h fan tachometer divisor 5xh the divisor values of the fan tachometer. 51h fan control 00h fan control registers 52h fan set x pwm control 00h fan pwm control register 58h vendor id 90h ite vendor id. read only register note: x indicates 1 or 2 or 3. 11.3.2.2 register description 11.3.2.2.1 configuration register (index=40h, default=08h) bit r/w description 7 r/w initialization. a ?1? restores all registers to thei r individual default values, except the serial bus address register. this bit clears itse lf when the default value is ?0?. 6 r/w on/off control of fan_ctl1. this bit is used to control fan_ctl1 when fan_ctl1 mode (bit 0 of the register index=51h) is set to on_off mode. 0: off. 1: on. 5-4 reserved 3 r/w int_clear. a ?1? disables the smi# and irq outputs wit h the contents of interr upt status bits remain unchanged. 2 r/w irq enables the irq interrupt output. 1 r/w smi# enable. a ?1? enabl es the smi# interrupt output. 0 r/w reserved 11.3.2.2.2 interrupt status register 1 (index=41h, default=00h) reading this register will clear itself following a read access. bit r/w description 7 r a ?1? indicates the fan count 2 limit has been reached. 6 r a ?1? indicates the fan count 1 limit has been reached. 5-0 - reserved
IT8673F 45 45 11.3.2.2.3 interrupt status register 2 (index=42h, default=00h) reading this register will clear itself after the read operation is completed. bit r/w description 7-5 - reserved 4 r a ?1? indicates a case open has occurred. 3 r a ?1? indicates the fanm count 3 limit has been reached. 2-0 - reserved 11.3.2.2.4 smi# mask register 1 (index=43h, default=00h) bit r/w description 7 r/w a ?1? disables the fanm count 2 interrupt status bit for smi#. 6 r/w a ?1? disables the fanm coun t 1 interrupt status bit for smi#. 5-0 r/w reserved 11.3.2.2.5 smi# mask register 2 (index=44h, default=00h) bit r/w description 7-5 - reserved 4 r/w a ?1? disables the case open intrusion interrupt status bit for smi#. 3 r/w a ?1? disables the fanm count 3 interrupt status bit for smi#. 2-0 r/w reserved 11.3.2.2.6 interrupt mask register 1 (index=45h, default=00h) bit r/w description 7 r/w a ?1? disables the fanm coun t 2 interrupt status bit for irq. 6 r/w a ?1? disables the fanm coun t 1 interrupt status bit for irq. 5-0 r/w reserved 11.3.2.2.7 interrupt mask register 2 (index=46h, default=0xh) bit r/w description 7 r/w a ?1? outputs an active high pulse on the case open pin (copen#). 6-5 - reserved 4 r/w a ?1? disables the case op en interrupt status bit for irq. 3 r/w a ?1? disables the fanm count 3 interrupt status bit for irq. 2-0 r/w reserved
IT8673F 46 46 11.3.2.2.8 fan tachometer divisor register (index=47h, default=5xh) bit r/w description 7-6 r/w fan tachometer count 2 divisor 00: divided by 1 01: divided by 2 10: divided by 4 11: divided by 8 5-4 r/w fan tachometer count 1 divisor 00: divided by 1 01: divided by 2 10: divided by 4 11: divided by 8 3-0 r reserved 11.3.2.2.9 fan control register (index=51h, default=00h) bit r/w description 7-6 r/w fan control registers set selection 00: fan_ctl1 01: fan_ctl2 10: fan_ctl3 11: reserved 5 - reserved. should be fixed at 0. 4 r/w on/off control of fan_ctl3. this bit is used to control fan_ctl3 when fan_ctl3 mode is set on on_off mode (bit 2 of this register is set to 0). 0: off. 1: on. 3 r/w on/off control of fan_ctl2. this bit is used to control fan_ctl2 when fan_ctl2 mode is set on on_off mode (bit 1 of this register is set to 0). 0: off. 1: on. 2 r/w fan_ctl3 mode. 0: on_off mode. 1: pwm mode. 1 r/w fan_ctl2 mode. 0: on_off mode. 1: pwm mode. 0 r/w fan_ctl1 mode. 0: on_off mode. 1: pwm mode. 11.3.2.2.10 fan set x pwm control register (index=52h, default=00h) the sex x is determined in the fan control register bits 7-6. bit r/w description 7 r/w reserved. should write a ?0?. 6-0 r/w pwm value. there are 128 steps of the fan_ ctl output pin are provided to control fan speeds.
IT8673F 47 47 11.3.3 operation 11.3.3.1 power on reset and software reset when the system power is first applied, the fan controller performs a ?power on reset? on the registers which are returned to default values (due to system hardware reset). 11.3.3.2 fan tachometer the fan tachometer inputs gate a 22.5 khz clock into an 8-bit counter (maximum count=255) for one period of the input signals. several divisors, located in fan divisor register, are provided for fan_tac1 and fan_tac2, and are used to modify the monitoring range. fan_tac3 is not adjustable, and its divisor value is always set to 2. counts are based on 2 pulses per resolution tachometer output. rpm = 1.35 x 10 6 / (count x divisor) the maximum input signal range is from 0 to vcc. the additional application is needed to clamp the input voltage and current. 11.3.3.3 fan controller on-off and smartguardian modes the IT8673F provides advanced fan controllers. two modes are provided for each controller: on_off and pwm modes. the former is a logical on or off, and the latter is a pwm output. with the addition of external application, the fan?s voltage values can be varied easily. 11.4 floppy disk controller (fdc) 11.4.1 introduction the floppy disk controller provides the interface between a host processor and up to two floppy disk drives. it integrates a controller and a digital data separator with write precompensation, data rate selection logic, microprocessor interface, and a set of registers. the fdc supports data transfer rates of 250 kbps, 300 kbps, 500 kbps, and 1 mbps. it operates in pc/at mode and supports 3-mode type drives. additionally, the fdc is software compatible with the 82077. the fdc configuration is handled by software and a set of configuration registers. status, data, and control registers facilitate the interface between the host microprocessor and the disk drive, providing information about the condition and/or state of the fdc. these configuration registers can select the data rate, enable interrupts, drives, and dma modes, and indicate errors in the data or operation of the fdc/fdd. the controller manages data transfers using a set of data transfer and control commands. these commands are handled in three phases: command, execution, and result. not all commands utilize all these three phases. 11.4.2 reset the IT8673F device implements both software and hardware reset options for the fdc. either type of the resets will reset the fdc, terminating all operations and placing the fdc into an idle state. a reset during a write to the disk will corrupt the data and the corresponding crc.
IT8673F 48 48 11.4.3 hardware reset (reset pin) when the fdc receives a reset signal, all registers of the fdc core are cleared (except those programmed by the specify command). to exit the reset state, the host must clear the dor bit. 11.4.4 software reset (dor reset and dsr reset) when the reset bit in the dor or the dsr is set, all registers of the fdc core are cleared. a reset performed by setting the reset bit in the dor has higher priority over a reset performed by setting the reset bit in the dsr. in addition, to exit the reset state, the dsr bit is self-clearing, while the host must clear the dor bit. 11.4.5 digital data separator the internal digital data separator is comprised of a digital pll and associated support circuitry. it is responsible for synchronizing the raw data signal read from the floppy disk drive. the synchronized signal is used to separate the encoded clock from the data pulses. 11.4.6 write precompensation write precompensation is a method that can be used to adjust the effects of bit shift on data as it is written to the disk. it is harder for the data separator to read data that has been subject to bit shifting. soft read errors can occur due to such bit shifting. write precompensation predicts where the bit shifting might occur within a data pattern and shifts the individual data bits back to their nominal positions. the fdc permits the selection of write precompensation via the data rate select register (dsr) bits 2 through 4. 11.4.7 data rate selection selecting one of the four possible data rates for the attached floppy disks is accomplished by setting the diskette control register (dcr) or data rate select register (dsr) bits to 0 and 1. the data rate is determined by the last value that is written to either the dcr or the dsr. when the data rate is set, the data separator clock is scaled appropriately. 11.4.8 status, data and control registers 11.4.8.1 digital output register (dor, fdc base address + 02h) this is a read/write register. it controls drive selection and motor enables as well as a software reset bit and dma enable. the i/o interface reset may be used at any time to clear the dor?s contents.
IT8673F 49 49 table 11-3. digital output register (dor) bit symbol name description 7-6 - - reserved 5 motb en drive b motor enable 0: disable drive b motor. 1: enable drive b motor. 4 mota en drive a motor enable 0: disable drive a motor. 1: enable drive a motor. 3 dmaen disk interrupt and dma enable 0: disable disk interrupt and dma (drqx, dackx#, tc and intx). 1: enable disk interrupt and dma. 2 reset# fdc function reset 0: reset fdc function. 1: clear reset of fdc function. this reset does not affect the dsr, dcr or dor. 1 - - reserved 0 dvsel drive selection 0: selects drive a. 1: selects drive b. 11.4.8.2 tape drive register (tdr, fdc base address + 03h) this is a read/write register and is included for 82077 software compatibility. the contents of this register are not used internal to the device. table 11-4. tape drive register (tdr) bit symbol name description 7-2 nu not used - 1-0 tp_sel[1:0] tape drive selection tp_sel[1:0] : drive selected. 00: none 01: 1 10: 2 11: 3 11.4.8.3 main status register (msr, fdc base address + 04h) this is a read only register. it indicates the general status of the fdc, and is able to receive data from the host. the msr should be read before each byte is sent to or received from the data register, except when in dma mode.
IT8673F 50 50 table 11-5. main status register (msr) bit symbol name description 7 rqm request for master fdc request for master. 0: the fdc is busy and cannot receive data from the host. 1: the fdc is ready and the host can transfer data. 6 dio data i/o direction indicates the direction of data tr ansfer once a rqm has been set. 0: write 1: read 5 ndm non-dma mode this bit selects non-dma mode of operation. 0: dma mode selected. 1: non-dma mode selected. this mode is selected via the specify command during the execution phase of a command. 4 cb diskette control busy indicates whether a command is in progress (the fdd is busy). 0: a command has been executed and the end of the result phase has been reached. 1: a command is being executed. 3-2 - - reserved 1 dbb drive b busy indicates whether driv e b is in the seek portion of a command. 0: not busy. 1: busy. 0 dab drive a busy indicates whether driv e a is in the seek portion of a command. 0: not busy. 1: busy. 11.4.8.4 data rate select register (dsr, fdc base address + 04h) this is a write only register. it is used to determine the data rate, amount of write precompensation, power down mode, and software reset. the data rate of the floppy controller is the most recent write of either the dsr or dcr. the dsr is unaffected by a software reset. the dsr can be set to 02h by a hardware reset, and the ?02h? represents the default precompensation, and 250 kbps indicates the data transfer rate.
IT8673F 51 51 table 11-6. data rate select register (dsr) bit symbol name description 7 s/w reset software reset software reset. it is active high and shares the same function with the reset# of the dor except that this bit is self-clearing. 6 power down power down when this bit is written with a ?1?, the floppy controller is put into manual low power mode. the clocks of the floppy co ntroller and data separator circuits will be turned off until a software reset or the data register or main status register is accessed. 5 nu not used - 4-2 pre-comp 2-0 precompensation select these three bits are used to determine the value of write precompensation that will be applied to the wdata# pin. track 0 is the default starting track number, which can be changed by the configure command for precompensation. pre_comp precompensation delay 111 001 010 011 100 101 110 000 0.0 ns 41.7 ns 83.3 ns 125.0 ns 166.7 ns 208.3 ns 250.0 ns default default precompensation delays data rate precompensation delay 1mbps 500kbps 300kbps 250kbps 41.7 ns 125.0 ns 125.0 ns 125.0 ns 1-0 drate1-0 data rate select bits 1-0 00 01 10 11 data transfer rate 500 kbps 300 kbps 250 kbps (default) 1 mbps 11.4.8.5 data register (fifo, fdc base address + 05h) this is an 8-bit read/write register. it transfers command information, diskette drive status information, and the result phase status between the host and the fdc. the fifo consists of several registers in a stack. only one register in the stack is permitted to transfer information or status to the data bus at a time. table 11-7. data register (fifo) bit symbol name description 7-0 data command information, diskette dr ive status, or result phase status data.
IT8673F 52 52 11.4.8.6 digital input register (dir, fdc base address + 07h) this is a read only register and shares this address with the diskette control register (dcr). table 11-8. digital input register (dir) bit symbol name description 7 dskchg diskette change indicates the inverting value of the bit monitored from the input of the floppy disk change pin (dskchg#). 6-0 nu not used - 11.4.8.7 diskette control register (dcr, fdc base address + 07h) this is a write only register and shares this address with the digital input register (dir). the dcr register controls the data transfer rate for the fdc. table 11-9. diskette control register (dcr) bit symbol name description 7-2 nu not used - 1-0 drate1-0 data rate select bits 1-0 00 01 10 11 data transfer rate 500kbps 300kbps 250kbps 1mbps 11.4.9 controller phases the fdc handles data transfer and control commands in three phases: command, execution and result. not all commands utilize all these three phases. 11.4.9.1 command phase upon reset, the fdc enters the command phase and is ready to receive commands from the host. the host must verify that msr bit 7 (rqm) = 1 and msr bit 6 (dio) = 0, indicating the fdc is ready to receive data. for each command, a defined set of command code and parameter bytes must be transferred to the fdc in a given order. see 11.4.11 and 11.4.12 for details on the various commands. rqm is set false (0) after each byte-read cycle, and set true (1) when a new parameter byte is required. the command phase is completed when this set of bytes has been received by the fdc. the fdc automatically enters the next controller phase and the fifo is disabled. 11.4.9.2 execution phase upon the completion of the command phase, the fdc enters the execution phase. it is in this phase that all data transfers occur between the host and the fdc. the specify command indicates whether this data transfer occurs in dma or non-dma mode. each data byte is transferred via an irqx or drqx# based upon the dma mode. on reset, the configure command can automatically enable or disable the fifo. the execution phase is completed when all data bytes have been received. if the command executed does not require a result phase, the fdc is ready to receive the next command.
IT8673F 53 53 11.4.9.3 result phase for commands that require data written to the fifo, the fdc enters the result phase when the irq or drq is activated. the msr bit 7 (rqm) and msr bit 6 (dio) must equal to 1 to read the data bytes. the result phase is completed when the host has read each of the defined set of result bytes for the given command. right after the completion of the phase, rqm is set to 1, dio is set to 0, and the msr bit 4 (cb) is cleared, indicating the fdc is ready to receive the next command. 11.4.9.4 result phase status registers for commands that contain a result phase, these read only registers indicate the status of the most recently executed command. table 11-10. status register 0 (st0) bit symbol name description 7-6 ic interrupt code 00: execution of the command has been completed correctly 01: execution of the command began, but failed to complete successfully 10: invalid command 11: execution of the command was not completed correctly, due to a polling error 5 se seek end the fdc executed a seek or re-calibrate command. 4 ec equipment check the tk00# pin was not set after a re-calibrate command was issued. 3 nu not used - 2 h head address the current head address. 1 dsb drive b select drive b selected. 0 dsa drive a select drive a selected.
IT8673F 54 54 table 11-11. status register 1 (st1) bit symbol name description 7 en end of cylinder indicates the fdc attempted to access a sector beyond the final sector of the track. this bit will be set if the terminal count (tc) signal is not issued after a read data or write data command. 6 nu not used - 5 de data error a crc error occurred in either the id field or the data field of a sector. 4 or overrun/ underrun an overrun on a read operation or underrun on a write operation occurs when the fdc is not serviced by the cpu or dma within the required time interval. 3 nu not used - 2 nd no data no data are available to the fdc when either of the following conditions is met: 1. the floppy disk cannot find the indicated sector while the read data or read deleted data commands are executed, or 2. while executing a read id command , an error occurs upon reading the id field, or 3. while executing a read a track command, the fdc cannot find the starting sector 1 nw not writeable set when a write data, write deleted data, or format a track command is being executed on a write-protected diskette. 0 ma missing address mark this flag bit is set when either of the following conditions is met: 1. the fdc cannot find a data address mark or a deleted data address mark on the specified track, or 2. the fdc cannot find any id address on the specified track after two index pulses are detected from the index# pin
IT8673F 55 55 table 11-12. status register 2 (st2) bit symbol name description 7 nu not used - 6 cm control mark this flag bit is set when either of the following conditions is met: 1. the fdc finds a deleted data address mark during a read data command, or 2. the fdc finds a data address mark during a read deleted data command 5 dd data error in data field this flag bit is set when a crc error is found in the data field. 4 wc wrong cylinder this flag bit is set when the track address in the id field is different from the track address specified in the fdc. 3 sh scan equal hit this flag bit is set when th e condition of "equal" is satisfied during a scan command. 2 sn scan not satisfied this flag bit is set when the fdc cannot find a sector on the cylinder during a scan command. 1 bc bad cylinder this flag bit is set when the track address equals ?ffh? and is different from the track address in the fdc. 0 md missing data address mark this flag bit is set when a data address mark or deleted data address mark cannot be found by the fdc. table 11-13. status register 3 (st3) bit symbol name description 7 ft fault indicates the current status of the fault signal from the fdd. 6 wp write protect indicates the current status of the write protect signal from the fdd. 5 rdy ready indicates the current status of the ready signal from the fdd. 4 tk0 track 0 indicates the current status of the track 0 signal from the fdd. 3 ts two side indicates the current status of the two side signal from the fdd. 2 hd head address indicates the current status of the head select signal to the fdd. 1-0 us1, us0 unit select indicate the current st atus of the unit select signals to the fdd.
IT8673F 56 11.4.10 command set the fdc utilizes a defined set of commands to communicate with the host. each command is comprised of a unique first byte, which contains the op-code, and a series of additional bytes, which contain the required set of parameters and results. the op-code byte indicates to the fdc how many additional bytes should be expected for the command being written. the descriptions use a common set of parameter byte symbols, which are presented in table 11-14. the fdc commands may be executed whenever the fdc is in the command phase. the fdc checks to see that the first byte is a valid command and, if so, proceeds. an interrupt is issued if it is not a valid command. table 11-14. command set symbol descriptions symbol name description c cylinder number the current/sel ected cylinder (t rack) number: 0 ? 255. d data the data pattern to be written into a sector. dc3 ? dc0 drive configuration bit3-0 designate which drives are perpend icular drives on the perpendicular mode command. dir direction control read/write head step direc tion control. 0 = step out; 1 = step in. dr0, dr1 disk drive select the selected drive number: 0 or 1. dtl data length when n is defined as 00h, dtl desi gnates the number of data bytes which users are going to read out or write into the sector. when n is not 00h, dtl is undefined. dfifo disable fifo a ?1? will disable the fifo (default). a ?0? will enable the fifo. ec enable count if ec=1, dtl of verify command will be sc. eis enable implied seek if eis=1, a seek operation will be performed before executing any read or write command that requires the c parameter. eot end of track the final sector number on a cylinder. during a read or write operation, the fdc stops data transfer after the sector number is equal to eot. gap2 gap 2 length by perpendicular mode comm and, this parameter changes gap 2 length in the format. gpl gap length the length of gap 3. during a fo rmat command, it determines the size of gap 3. h head address the head number 0 or 1, as spec ified in the sector id field. (h = hd in all command words.) hd head the selected head number 0 or 1. also controls the polarity of hdsel#. (h = hd in all command words.) hlt head load time the head load time in the fdd (2 to 254 ms in 2 ms increments). hut head unload time the head unload time after a read or write operation has been executed (16 to 240 ms in 16 ms increments). lock if lock=1, dfifo, fifothr, and pretrk parameters of the configure command will not be affected by a software reset. if lock=0 (default), the above parameters will be set to their default values following a software reset.
IT8673F 57 table 11-14. command set symbol descriptions (cont?d) symbol name description mfm fm or mfm mode if mfm is low, fm mode (si ngle density) is selected. if mfm is high, mfm mode (double density) is selected. mt multi-track if mt is high, a multi-track operation is to be performed. in this mode, the fdc will automatically start searching for sector 1 on side 1 after finishing a read/write operation on the last sector on side 0. n number the number of data byte s written into a sector, where: 00 = 128 bytes (pc standard) 01 = 256 bytes 02 = 512 bytes ? 07 = 16 kbytes ncn new cylinder number a new cylinder number, which is to be reached as a result of the seek operation. desired position of head. nd non-dma mode when nd is high, the fdc operates in the non-dma mode. ow overwrite if ow=1, dc3-0 of the perpendicular mode command can be modified. otherwise, those bits cannot be changed. pcn present cylinder number the cylinder number at the completion of a sense interrupt status command. position of head at present time. polld polling disable if polld=1, the in ternal polling routine is disabled. pretrk precompensation starting track number programmable from track 0 ? 255. r record the sector number, which will be read or written. rcn relative cylinder number to determine the relative cylinder offset from present cylinder as used by the relative seek command. sc the number of sectors per cylinder. sk skip if sk=1, the read data operation will skip sectors with a deleted data address mark. or, the read deleted data operation only accesses sectors with a deleted data address mark. srt step rate time the stepping rate for the fdd (1 to 16 ms in 1 ms increments). stepping rate applies to all drives (f=1 ms, e=2 ms, etc.). st0 st1 st2 st3 status 0 status 1 status 2 status 3 st0 ? 3 stand for one of four registers that store the status information after a command has been executed. this information is available during the result phase after command execution. these registers should not be confused with the main status register (selected by a 0 = 0); st0 ? 3 may be read only after a command has been executed and contai n information associated with that particular command. stp if stp = 1 during a scan operation, the data in contiguous sectors are compared byte by byte with data sent from the pr ocessor (or dma). if stp = 2, alternate sectors are read and compared.
IT8673F 58 table 11-15. command set summary read data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds dr1 dr0 w c w h w r w n w eot w gpl command w dtl sector id information before the command execution execution data transfer between the fdd and the main system r st0 r st1 r st2 status information after command execution r c r h r r result r n sector id information after command execution read deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds dr1 dr0 w c w h sector id information before the command execution w r w n w eot w gpl command w dtl execution data transfer between the fdd and the main system r st0 r st1 status information after command execution r st2 r c r h sector id information after command execution r r result r n
IT8673F 59 read a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds dr1 dr0 w c w h sector id information before the command execution w r w n w eot w gpl command w dtl execution data transfer between the fdd and main system cylinder's contents from index hole to eot r st0 r st1 sector id information before the command execution r st2 r c r h sector id information after command execution r r result r n write data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds dr1 dr0 w c w h sector id information before the command execution w r w n w eot w gpl command w dtl execution data transfer between the fdd and the main system r st0 r st1 status information after command execution r st2 r c r h sector id information after command execution r r result r n
IT8673F 60 write deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds dr1 dr0 w c w h sector id information before the command execution w r w n w eot w gpl command w dtl execution data transfer between the fdd and the main system. r st0 r st1 status information after command execution r st2 r c r h sector id information after command execution r r result r n format a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds dr1 dr0 w n bytes/sector w sc sectors/cylinder w gpl gap 3 command w d filler byte w c w h w r execution w n input sector parameters per-sector r st0 r st1 r st2 fdc formats an entire cylinder status information after command execution r undefined r undefined r undefined result r undefined
IT8673F 61 scan equal data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm sk 1 0 0 0 1 command codes w 0 0 0 0 0 hds dr1 dr0 w c w h sector id information before the command execution w r w n w eot w gpl command w stp execution data transferred from the system to controller is compared to data read from disk r st0 r st1 status information after command execution r st2 r c r h sector id information after command execution r r result r n scan low or equal data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm sk 1 1 0 0 1 command codes w 0 0 0 0 0 hds dr1 dr0 w c w h sector id information before the command execution w r w n w eot w gpl command w stp execution data transferred from the system to controller is compared to data read from disk r st0 r st1 status information after command execution r st2 r c r h sector id information after command execution r r result r n
IT8673F 62 scan high or equal data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm sk 1 1 1 0 1 command codes w 0 0 0 0 0 hds dr1 dr0 w c w h sector id information before the command execution w r w n w eot w gpl command w stp execution data transferred from the system to controller is compared to data read from disk r st0 r st1 status information after command execution r st2 r c r h sector id information after command execution r r result r n verify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds dr1 dr0 w c w h sector id information before the command execution w r w n w eot w gpl command w dtl/sc execution no data transfer takes place r st0 r st1 status information after command execution r st2 r c r h sector id information after command execution r r result r n
IT8673F 63 read id data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w 0 mfm 0 0 1 0 1 0 command codes command w 0 0 0 0 0 hds dr1 dr0 execution the first correct id information on the cylinder is stored in the data register r st0 r st1 status information after command execution r st2 r c r h sector id information during execution phase r r result r n configure data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w 0 0 0 1 0 0 1 1 configure information w 0 0 0 0 0 0 0 0 w 0 eis dfifo polld fifothr command pretrk execution re-calibrate data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w 0 0 0 0 0 1 1 1 command codes command w 0 0 0 0 0 0 dr1 dr0 execution head retracted to track 0 seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w 0 0 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds dr1 dr0 command w ncn execution head is positioned over proper cylinder on diskette
IT8673F 64 relative seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w 1 dir 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds dr1 dr0 command w rcn execution head is stepped in or out a programmable number of tracks dumpreg data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 0 command codes execution registers placed in fifo r pcn-drive 0 r pcn-drive 1 r pcn-drive 2 r pcn-drive 3 r srt hut r hlt nd r r lock 0 dc3 dc2 dc1 dc0 gap wg r 0 dis dfifo polld fifothr result r pretrk lock data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command codes result r 0 0 0 lock 0 0 0 0 version data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 0 0 command codes result r 1 0 0 1 0 0 0 0 enhanced controller sense interrupt status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 0 0 0 command codes r st0 result r pcn status information at the end of each seek operation
IT8673F 65 sense drive status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 0 0 command codes w 0 0 0 0 0 hds dr1 dr0 result r st3 status information about fdd specify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w 0 0 0 0 0 0 1 1 command codes w srt hut command w hlt nd perpendicular mode data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w 0 0 0 1 0 0 1 0 command codes command w ow 0 dc3 dc2 dc1 dc0 gap wg invalid data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w invalid codes invalid command codes (no-op: fdc goes into standby state) result r st0 st0 = 80h
IT8673F 66 11.4.11 data transfer commands all data transfer commands utilize the same parameter bytes (except for format a track command) and return the same result data bytes. the only difference between them is the five bits (0 ? 4) of the first byte. 11.4.11.1 read data the read data command contains nine command bytes that place the fdc into the read data mode. each read operation is initialized by a read data command. the fdc locates the sector to be read by matching id address marks and id fields from the command with the information on the diskette. the fdc then transfers the data to the fifo. when the data from the given sector has been read, the read data command is completed and the sector address is automatically incremented by ?1?. the data from the next sector is read and transferred to the fifo in the same manner. such a continuous read function is called a "multi-sector read operation". if a tc or an implied tc (fifo overrun/underrun) is received, the fdc stops sending data, but continues to read data from the current sector and checks the crc bytes until the end of the sector is reached and the read operation is completed. the sector size is determined by the n parameter value as calculated in the equation below: sector size = 2 (7+n value) bytes. the dtl parameter determines the number of bytes to be transferred. therefore, if n = 00h, setting the sector size to 128 and the dtl parameter value is less than this, the remaining bytes will be read and checked for crc errors by the fdc. if this occurs in a write operation, the remaining bytes will be filled with 0. if the sector size is not 128 (n > 00h), dtl should be set to ffh. in addition to performing multi-sector read operations, the fdc can perform multi-track read operations. when the mt parameter is set, the fdc can read both sides of a disk automatically. the combination of n and mt parameter values determines the amount of data that can be transferred during either type of read operation. table 11-16 shows the maximum data transfer capacity and the final sector the fdc reads based on these parameters. table 11-16. effects of mt and n bits mt n maximum transfer capacity final sector read from disk 0 1 256 x 26 = 6656 26 on side 0 or side 1 1 1 256 x 52 = 13312 26 on side 1 0 2 512 x 15 = 7680 15 on side 0 or side 1 1 2 512 x 30 = 15360 15 on side 1 0 3 1024 x 8 = 8192 8 on side 0 or side 1 1 3 1024 x16 =16384 16 on side 1
IT8673F 67 11.4.11.2 read deleted data the read deleted data command is the same as the read data command, except that a deleted data address mark (as opposed to a data address mark) is read at the beginning of the data field. this command is typically used to mark a bad sector on a diskette. 11.4.11.3 read a track after receiving a pulse from the index# pin, the read a track command reads the entire data field from each sector of the track as a continuous block. if any id or data field crc error is found, the fdc continues to read data from the track and indicates the error at the end. because the multi-track [and skip] operation[s] is[are] not allowed under this command, the mt and sk bits should be low (0) during the command execution. this command terminates normally when the number of sectors specified by eot has not been read. if, however, no id address mark has been found by the second occurrence of the index pulse, the fdc will set the ic code in the st0 to 01, indicating an abnormal termination, and then finish the command. 11.4.11.4 write data the write data command contains nine command bytes that place the fdc into the write data mode. each write operation is initialized by a write data command. the fdc locates the sector to be written by reading id fields and matching the sector address from the command with the information on the diskette. then the fdc reads the data from the host via the fifo and writes the data into the sector?s data field. finally, the fdc computes the crc value, storing it in the crc field, and increments the sector number (stored in the r parameter) by ?1?. the next data field is written into the next sector in the same manner. such a continuous write function is called a "multi-sector write operation". if a tc or an implied tc (fifo overrun/underrun) is received, the fdc stops writing data and fills the remaining data field with 0s. if a check of the crc value indicates an error in the sector id field, the fdc will set the ic code in the st0 to 01 and the de bit in the st1 to 1, indicating an abnormal termination, and then terminate the write data command. the maximum data transfer capacity and the dtl, n, and mt parameters are the same as in the read data command. 11.4.11.5 write deleted data the write deleted data command is the same as the write data command, except that a deleted data address mark (instead of a data address mark) is written at the beginning of the data field. this command is typically used to mark a bad sector on a diskette. 11.4.11.6 format a track the format a track command is used to format an entire track. initialized by an index pulse, it writes data to the gaps, address marks, id fields and data fields according to the density mode selected (fm or mfm). the gap and data field values are controlled by the host-specified values programmed into n, sc, gpl, and d during the command phase. the data field is filled with the data byte specified by d. the four data bytes per sector (c, h, r, and n) needed to fill the id field are supplied by the host. the c, r, h, and n values must be renewed for each new sector of a track. only the r parameter value must be changed when a sector is formatted, allowing the disk to be formatted with non-sequential sector addresses. these steps are repeated until a new index pulse is received, at which point the format a track command is terminated.
IT8673F 68 11.4.11.7 scan the scan command allows the data read from the disk to be compared with the data sent from the system. there are three scan commands: scan equal disk data = system data scan high or equal disk data system data scan low or equal disk data system data the scan command execution continues until the scan condition has been met, or the eot has been reached, or if tc is asserted. read errors on the disk have the same error condition as the read data command. if the sk bit is set, sectors with deleted data address marks are ignored. if all sectors read are skipped, the command terminates with the d3 bit of the st2 being set. the result phase of the command is shown below: table 11-17. scan command result status register command d2 d3 condition 0 1 disk = system scan equal 1 0 disk system 0 1 disk = system 0 0 disk > system scan high or equal 1 0 disk < system 0 1 disk = system 0 0 disk < system scan low or equal 1 0 disk > system 11.4.11.8 verify the verify command is used to read logical sectors containing a normal data am from the selected drive without transferring the data to the host. this command acts like a read data command except that no data is transferred to the host. this command is designed for post-format or post write verification. data is read from the disk, as the controller checks for valid address marks in the address and data fields. the crc is computed and checked against the previously stored value. because no data is transferred to the host, the tc (terminal count of dma) cannot be used to terminate this command. an implicit tc will be issued to the fdc by setting the ec bit. this implicit tc will occur when the sc value has decremented to 0. this command can also be terminated by clearing the ec bit and when the eot value equals to the final sector to be checked.
IT8673F 69 table 11-18. verify command result mt ec sc/eot termination result 0 0 sc = dtl eot # sectors per side no error 0 0 sc = dtl eot > # sectors per side abnormal termination 0 1 sc # sectors remaining and eot # sectors per side no error 0 1 sc > # sectors remaining or eot > # sectors per side abnormal termination 1 0 sc = dtl eot > # sectors per side no error 1 0 sc = dtl eot > # sectors per side abnormal termination 1 1 sc # sectors remaining and eot # sectors per side no error 1 1 sc > # sectors remaining or eot > # sectors per side abnormal termination 11.4.12 control commands the control commands do not transfer any data. instead, these commands are used to monitor and manage the data transfer. three of the control commands generate an interrupt when finished ? read id, re-calibrate and seek. it is strongly recommended that a sense interrupt status command be issued after these commands to capture their valuable interrupt information. the re-calibrate, seek, and specify commands do not return any result bytes. 11.4.12.1 read id the read id command is used to find the actual recording head position. it stores the first readable id field value into the fdc registers. if the fdc cannot find an id address mark by the time a second index pulse is received, an abnormal termination will be generated by setting the ic code in the st0 to 01. 11.4.12.2 configure the configure command determines some special operation modes of the controller. it needs not to be issued if the default values of the controller meet the system requirements. eis: enable implied seeks. a seek operation is performed before a read, write, scan, or verify commands. 0 = disabled (default). 1 = enabled. dfifo: disable fifo. 0 = enabled. 1 = disabled (default). polld: disable polling of the drives.
IT8673F 70 0 = enabled (default). when enabled, a single interrupt is generated after a reset. 1 = disabled. fifothr: the fifo threshold in the execution phase of data transfer commands. they are programmable from 00 to 0f hex (1 bytes to 16 bytes). defaults to one byte. pretrk: the pre-compensation start track number. they are programmable from track 0 to ff hex (track 0 to track 255). defaults to track 0. 11.4.12.3 re-calibrate the re-calibrate command retracts the fdc read/write head to the track 0 position, resetting the value of the pcn counter and checking the tk00# status. if tk00# is low, the dir# pin remains low and step pulses are issued. if tk00# is high, se [and ec bits] of st0 are set high, and the command is terminated. when tk00# remains low for 79 step pulses, the re-calibrate command is terminated by setting se and ec bits of st0 high. consequently, for disks that can accommodate more than 80 tracks, more than one re-calibrate command is required to retract the head to the physical track 0. the fdc is in a non-busy state during the execution phase of this command, making it possible to issue another re-calibrate command in parallel with the current command. on power-up, software must issue a re-calibrate command to properly initialize the fdc and the drives attached. 11.4.12.4 seek the seek command controls movement of the fdc read/write head movement from one track to another. the fdc compares the current head position, stored in pcn, with ncn values after each step pulse to determine what direction to move the head, if required. the direction of movement is determined below: pcn < ncn ? step in: sets dir# signal to 1 and issues step pulses, pcn > ncn ? step out: sets dir# signal to 0 and issues step pulses, and pcn = ncn ? terminate the command by setting the st0 se bit to 1. the impulse rate of step pulse is controlled by stepping rate time (srt) bit in the specify command. the fdc is in a non-busy state during the execution phase of this command, making it possible to issue another seek command in parallel with the current command. 11.4.12.5 relative seek the relative seek command steps the selected drive in or out in a given number of steps. the dir bit is used to determine to step in or out. rcn (relative cylinder number) is used to determine how many tracks to step the head in or out from the current track. after the step operation is completed, the controller generates an interrupt, but the command has no result phase. no other command except the sense interrupt status command should be issued while a relative seek command is in progress. 11.4.12.6 dumpreg the dumpreg command is designed for system run-time diagnostics, and application software development, and debug. this command has one byte of command phase and 10 bytes of result phase, which return the values of parameters set in other commands.
IT8673F 71 11.4.12.7 lock the lock command allows the programmer to fully control the fifo parameters after a hardware reset. if the lock bit is set to 1, the parameters dfifo, fifothr, and pretrk in the configure command are not affected by a software reset. if the bit is set to 0, those parameters are set to default values after a software reset. 11.4.12.8 version the version command is used to determine the controller being used. in result phase, a value of 90 hex is returned in order to be compatible with the 82077. 11.4.12.9 sense interrupt status the sense interrupt status command resets the interrupt signal (irq) generated by the fdc, and identifies the cause of the interrupt via the ic code and se bit of the st0, as shown in table 11-19. it may be necessary to generate an interrupt when any of the following conditions occur: 1. before any data transfer or read id command 2. after seek or re-calibrate commands (no result phase exists) 3. when a data transfer is required during an execution phase in the non-dma mode table 11-19. interrupt identification se ic code cause of interrupt 0 11 polling. 1 00 normal termination of seek or re-calibrate command. 1 01 abnormal termination of seek or re-calibrate command. 11.4.12.10 sense drive status the sense drive status command acquires drive status information. it has no execution phase. 11.4.12.11 specify the specify command sets the initial values for the hut (head unload time), hlt (head load time), srt (step rate time), and nd (non-dma mode) parameters. the possible values for hut, srt, and hlt are shown in table 11-20, table 11-21 and table 11-22 respectively. the fdc is operated in dma or non-dma mode based on the value specified by the nd parameters. table 11-20. hut values parameter 1 mbps 500 kbps 300 kbps 250 kbps 0 128 256 426 512 1 8 16 26.7 32 ? ? ? ? ? e 112 224 373 448 f 120 240 400 480
IT8673F 72 table 11-21. srt values parameter 1 mbps 500 kbps 300 kbps 250 kbps 0 8 16 26.7 32 1 7.5 15 25 30 ? ? ? ? ? e 1 2 3.33 4 f 0.5 1 1.67 2 table 11-22. hlt values parameter 1 mbps 500 kbps 300 kbps 250 kbps 00 128 256 426 512 01 1 2 3.33 4 02 2 4 6.7 8 ? ? ? ? ? 7e 126 252 420 504 7f 127 254 423 508 11.4.12.12 perpendicular mode the perpendicular mode command is used to support the unique read/write/format commands of perpendicular recording disk drives (4 mbytes unformatted capacity). this command configures each of the four logical drives as a perpendicular or conventional disk drive via the dc3-dc0 bits, or with the gap and wg control bits. perpendicular recording drives operate in ?extra high density? mode at 1mbps, and are downward compatible with 1.44 mbyte and 720 kbyte drives at 500 kbps (high density) and 250 kbps (double density) respectively. this command should be issued during the initialization of the floppy disk controller. then, when a drive is accessed for a format a track or write data command, the controller adjusts the format or write data parameters based on the data rate. if wg and gap are used (not set to 00), the operation of the fdc is based on the values of gap and wg. if wg and gap are set to 00, setting dcn to 1 will set drive n to perpendicular mode. dc3-dc0 are unaffected by a software reset, but wg and gap are both cleared to 0 after a software reset. table 11-23. effects of gap and wg on format a track and write data commands gap wg mode length of gap2 format field portion of gap2 re-written by write data command 0 0 conventional 22 bytes 0 bytes 0 1 perpendicular (500 kbps) 22 bytes 19 bytes 1 0 reserved (conventional) 22 bytes 0 bytes 1 1 perpendicular (1 mbps) 41 bytes 38 bytes
IT8673F 73 table 11-24. effects of drive mode and data rate on format a track and write data commands data rate drive mode length of gap2 format field portion of gap2 re-written by write data command 250/300/500 kbps conventional perpendicular 22 bytes 22 bytes 0 bytes 19 bytes 1 mbps conventional perpendicular 22 bytes 41 bytes 0 bytes 38 bytes 11.4.12.13 invalid the invalid command indicates when an undefined command has been sent to fdc. the fdc will set the bit 6 and the bit 7 in the main status register to 1 and terminate the command without issuing an interrupt. 11.4.13 dma transfers dma transfers are enabled by the specify command and are initiated by the fdc by activating the drq cycle during a data transfer command. the fifo is enabled directly by asserting the dma cycles. 11.4.14 low power mode when writing a 1 to the bit 6 of the dsr, the controller is set to low power mode immediately. all the clock sources including data separator, microcontroller, and write precompensation unit will be gated. the fdc can be resumed from the low-power state in two ways. one is a software reset via the dor or dsr; and the other is a read or write to either the data register or main status register. the second method is more preferred since all internal register values are retained.
IT8673F 74 11.5 serial port (uart) description the IT8673F incorporates two enhanced serial ports that perform serial to parallel conversion on received data, and parallel to serial conversion on transmitted data. each of the serial channels individually contains a programmable baud rate generator which is capable of dividing the input clock by a number ranging from 1 to 65535. the data rate of each serial port can also be programmed from 115.2k baud down to 50 baud. the character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd, stick or no parity; and privileged interrupts. table 11-25. serial channel registers register dlab* address read write data 0 base + 0h rbr (receiver buffer register) tbr (transmitter buffer register) control 0 x x x 1 1 base + 1h base + 2h base + 3h base + 4h base + 0h base + 1h ier (interrupt e nable register) iir (interrupt identification register) lcr (line control register) mcr (modem control register) dll (divisor latch lsb) dlm (divisor latch msb) ier fcr (fifo control register) lcr mcr dll dlm status x x x base + 5h base + 6h base + 7h lsr (line status register) msr (modem status register) scr (scratch pad register) lsr msr scr * dlab is bit 7 of the line control register. 11.5.1 data registers the tbr and rbr individually hold from five to eight data bits. if the transmitted data is less than eight bits, it aligns to the lsb. either received or transmitted data is buffered by a shift register, and is latched first by a holding register. the bit 0 of any word is first received and transmitted. (1) receiver buffer register (rbr) (read only, address offset=0, dlab=0) this register receives and holds the incoming data. it contains a non-accessible shift register which converts the incoming serial data stream into a parallel 8-bit word. (2) transmitter buffer register (tbr) (write only, address offset=0, dlab=0) this register holds and transmits the data via a non-accessible shift register, and converts the outgoing parallel data into a serial stream before transmission. 11.5.2 control registers: ier, iir, fcr, dll, dlm, lcr and mcr (1) interrupt enable register (ier) (read/write, address offset=1, dlab=0) the ier is used to enable (or disable) four active high interrupts which activate the interrupt outputs with its lower four bits: ier(0), ier(1), ier(2), and ier(3).
IT8673F 75 table 11-26. interrupt enable register description bit default description 7-4 - reserved 3 0 enable modem status interrupt sets this bit high to enable the modem status interrupt when one of the modem status registers changes its bit status. 2 0 enable receiver line status interrupt sets this bit high to enable the receiver line status interrupt which is caused when overrun, parity, framing or break occurs. 1 0 enable transmitter holding register empty interrupt sets this bit high to enable the transmitter holding register empty interrupt. 0 0 enable received data available interrupt sets this bit high to enable the received data available interrupt and time-out interrupt in the fifo mode. (2) interrupt identification register (iir) (read only, address offset=2) this register facilitates the host cpu to determine interrupt priority and its source. the priority of four existing interrupt levels is listed below: 1. received line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) when a privileged interrupt is pending and the type of interrupt is stored in the iir which is accessed by the host, the serial channel holds back all interrupts and indicates the pending interrupts with the highest priority to the host. any new interrupts will not be acknowledged until the host access is completed. the contents of the iir are described in the table on the next page:
IT8673F 76 table 11-27. interrupt identification register fifo mode interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt so urce interrupt reset control 0 x x 1 - none none - 0 1 1 0 first receiver line status oe, pe, fe, or bi read lsr 0 1 0 0 second received data available received data available read rbr or fifo drops below the trigger level 1 1 0 0 second character time-out indication no characters have been removed from or input to the rcvr fifo during the last 4 character times and there is at least 1 character in it during this time read rbr 0 0 1 0 third transmitter holding register empty transmitter holding register empty read iir if thre is the interrupt source write thr 0 0 0 0 fourth modem status cts#, dsr#, ri#, dcd# read msr note : x = not defined iir(7), iir(6): are set when fcr(0) = 1. iir(5), iir(4): always logic 0. iir(3): in non-fifo mode, this bit is a logic 0. in the fifo mode, this bit is set along with bit 2 when a time-out interrupt is pending. iir(2), iir(1): used to identify the highest priority interrupt pending. iir(0): used to indicate a pending interrupt in either a hard-wired prioritized or polled fan with a logic 0 state. in such a case, iir contents may be used as a pointer to the appropriate interrupt service routine.
IT8673F 77 (3) fifo control register (fcr) (write only, address offset=2) this register is used to enable/clear the fifo, and set the rcvr fifo trigger level. table 11-28. fifo control register description bit default description 7-6 - receiver trigger level select these bits set the trigger levels for the rcvr fifo interrupt. 5-4 0 reserved 3 0 this bit doesn't affect the serial channel operation. rxrdy and txrdy functions are not available on this chip. 2 0 transmitter fifo reset this self-clearing bit clears all contents of the xmit fifo and resets its related counter to 0 via a logic "1." 1 0 receiver fifo reset setting this self-clearing bit to a logic ?1? clears all contents of the rcvr fifo and resets its related counter to 0 (except the shift register). 0 0 fifo enable xmit and rcvr fifo are enabled when this bit is set high. xmit and rcvr fifos are disabled and cleared respectively when this bit is cleared to low. this bit must be a logic 1 if the other bits of the fcr are written to, or they will not be properly programmed. when this register is switched to non-fifo mode, all its contents are cleared. table 11-29. receiver fifo trigger level encoding fcr (7) fcr (6) rcvr fifo trigger level 0 0 1 byte 0 1 4 bytes 1 0 8 bytes 1 1 14 bytes (4) divisor latches (dll, dlm) (read/write, address offset=0,1, dlab=0) two 8-bit divisor latches (dll and dlm) store the divisor values in a 16-bit binary format. they are loaded during the initialization to generate a desired baud rate. (5) baud rate generator (brg) each serial channel contains a programmable brg which can take any clock input (from dc to 3 mhz) to generate standard ansi/ccitt bit rates for the channel clocking with an external clock oscillator. the dll or dlm is a number of 16-bit format, providing the divisor range from 1 to 2 16 to obtain the desired baud rate. the output frequency is 16x data rate.
IT8673F 78 table 11-30. baud rates using (24 mhz 13) clock desired baud rate divisor used 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 (6) scratch pad register (read/write, address offset=7) this 8-bit register does not control the uart operation in any way. it is intended as a scratch pad register to be used by programmers to temporarily hold general purpose data. (7) line control register (lcr) (read/write, address offset=3) lcr controls the format of the data character and supplies the information of the serial line. its contents are described on the next page:
IT8673F 79 table 11-31. line control register description bit default description 7 0 divisor latch access bit (dlab) must be set to high to access the divisor latches of the baud rate generator during read or write operations. it must be set low to access the data register (rbr and tbr) or the interrupt enable register. 6 0 set break forces the serial output (sout) to the spacing state (logic 0) by a logic 1, and this state will be preserved until a low level resetting lcr(6), enabling the serial port to alert the terminal in a communication system. 5 0 stick parity when this bit and lcr(3) are high at the same time, the parity bit is transmitted, and then detected by receiver, in opposite state by lcr(4) to force the parity bit into a known state and to check the parity bit in a known state. 4 0 even parity select when parity is enabled (lcr(3) = 1), lcr(4) = 0 selects odd parity, and lcr(4) = 1 selects even parity. 3 0 parity enable a parity bit, located between the last data word bit and stop bit, will be generated or checked (transmit or receive data) when lcr(3) is high. 2 0 number of stop bits specifies the number of stop bits in each serial character, as summarized in table 11-32. 1-0 00 word length select [1:0] 11: 8 bits 10: 7 bits 01: 6 bits 00: 5 bits table 11-32. stop bits number encoding lcr (2) word length no. of stop bits 0 - 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2 note : the receiver will ignore all stop bits beyond the first, regardless of the number used in transmission.
IT8673F 80 (8) modem control register (mcr) (read/write, address offset=4) controls the interface by the modem or data set (or device emulating a modem). table 11-33. modem control register description bit default description 7-5 - reserved 4 0 internal loop back provides a loopback feature for diagnostic test of the serial channel when it is set high. serial output (sout) is set to the marking state shift register output loops back into the receiver shift register. all modem control inputs (cts#, dsr#, ri# and dcd#) are disconnected. the four modem control outputs (dtr#, rts#, out1 and out2) are internally connected to the four modem control inputs and forced to inactive high. the transmitted data are then immediately received, allowing the processor to verify the transmit and receive data path of the serial channel. 3 0 out2 this bit is the output 2 bit and enables the serial port interrupt output by a logic 1. 2 0 out1 this bit does not have an output pin and can only be read or written by the cpu. 1 0 request to send (rts) controls the request to send (rts#) which is in an inverse logic state with mcr(1). 0 0 data terminal ready (dtr) controls the data terminal ready (dtr#) which is in an inverse logic state with the mcr(0).
IT8673F 81 11.5.3 status registers: lsr and msr (1) line status register (lsr) (read/write, address offset=5) this register provides status indications and is usually the first register read by the cpu to determine the cause of an interrupt or to poll the status of each serial channel. the contents of the lsr are described below: table 11-34. line status register description bit default description 7 0 error in receiver fifo in 16450 mode, this bit is always 0. in the fifo mode, it sets high when there is at least one parity error, framing or break interrupt in the fifo. this bit is cleared when the cpu reads the lsr, if there are no subsequent errors in the fifo. 6 1 transmitter empty this read only bit indicates that the transmitter holding register and transmitter shift register are both empty. otherwise, this bit is "0," and has the same function in the fifo mode. 5 1 transmitter holding register empty transmitter holding register empty (thre). this read only bit indicates that the tbr is empty and is ready to accept a new character for transmission. it is set high when a character is transferred from the thr into the transmitter shift register, causing a priority 3 iir interrupt which is cleared by a read of iir. in the fifo mode, it is set when the xmit fifo is empty and is cleared when at least one byte is written to the xmit fifo. 4 0 line break break interrupt (bi) status bit indicates that the last character received was a break character, (invalid but entire character), including parity and stop bits. this occurs when the received data input is held in the spacing (logic 0) for longer than a full word transmission time (start bit + data bits + parity + stop bit). when any of these error conditions is detected (lsr(1) to lsr(4)), a receiver line status interrupt (priority 1) will be generated in the iir with the ier(2) enabled previously. 3 0 framing error framing error (fe) bit, a logic 1, indicates that the stop bit in the received character was not valid. it resets low when the cpu reads the contents of the lsr. 2 0 parity error the parity error (pe) indicates by with a logic 1 that the received data character does not have the correct even or odd parity, as selected by lcr(4). it will be reset to "0" whenever the lsr is read by the cpu. 1 0 overrun error overrun error (oe) bit indicates by a logic 1 that the rbr has been overwritten by the next character before it had been read by the cpu. in the fifo mode, the oe occurs when the fifo is full and the next character has been completely received by the shift register. it will be reset when the lsr is read by the cpu. 0 0 data ready a "1" indicates a character has been received by the rbr. and a logic "0" indicates all the data in the rbr or the rcvr fifo have been read.
IT8673F 82 (2) modem status register (msr) (read/write, address offset=6) this 8-bit register indicates the current state of the control lines with modems or peripheral devices in addition to this current state information. four of these eight bits msr(4) - msr(7) can provide the state change information when a modem control input changes state. it is reset low when the host reads the msr. table 11-35. modem status register descriptiopn bit default description 7 0 data carrier detect data carrier detect - indicates the complement status of data carrier detect (dcd#) input. if mcr(4) = 1, msr(7) is equivalent to out2 of the mcr. 6 0 ring indicator ring indicator (ri#) - indicates the complement status to the ri# input. if mcr(4)=1, msr(6) is equivalent to out1 in the mcr. 5 0 data set ready data set ready (dsr#) - indicates that the modem is ready to provide received data to the serial channel receiver circuitry. if the serial channel is in the loop mode (mcr(4) = 1), msr(5) is equivalent to dtr# in the mcr. 4 0 clear to send clear to send (cts#) - indicates the complement of cts# input. when the serial channel is in the loop mode (mcr(4)=1), msr(5) is equivalent to rts# in the mcr. 3 0 delta data carrier detect indicates that the dcd# input state has been changed since the last time read by the host. 2 0 trailing edge ring indicator indicates that the ri input state to the serial channel has been changed from a low to high since the last time read by the host. the change to logic 1 does not activate the teri. 1 0 delta data set ready delta data set ready (ddsr) - a logic "1" indicates that the dsr# input state to the serial channel has been changed since the last time read by the host. 0 0 delta clear to send this bit indicates the cts# input to the chip has changed state since the last time the msr was read.
IT8673F 83 11.5.4 reset the reset of the IT8673F should be held to an idle mode reset high for 500 ns until initialization, and this causes the initialization of the transmitter and receiver internal clock counters. table 11-36. reset control of registers and pinout signals register/signal reset control reset status interrupt enable register interrupt identifi cation register fifo control register line control register modem control register line status register modem status register sout1, sout2 rts0#, rts1#, dtr0#, dtr1# irq of serial port reset reset reset reset reset reset reset reset reset reset all bits low bit 0 is high and bits 1-7 are low all bits low all bits low all bits low bits 5 and 6 are high, others are low bits 0-3 low, bits 4-7 input signals high high high impedance 11.5.5 programming each serial channel of the IT8673F is programmed by control registers, whose contents define the character length, number of stop bits, parity, baud rate and modem interface. even though the control register can be written in any given order, the ier should be the last register written because it controls the interrupt enables. after the port has been programmed, these registers can still be updated whenever the port is not transferring data. 11.5.6 software reset this approach allows the serial port returning to a completely known state without a system reset. this is achieved by writing the required data to the lcr, dll, dlm and mcr. the lsr and rbr must be read before enabling interrupts to clear out any residual data or status bits that may be invalid for subsequent operations. 11.5.7 clock input operation the input frequency of the serial channel is 24 mhz 13, not exactly 1.8432 mhz. 11.5.8 fifo interrupt mode operation (1) rcvr interrupt when setting fcr(0)=1 and ier(0)=1, the rcvr fifo and receiver interrupts are enabled. the rcvr interrupt occurs under the following conditions: a. the receive data available interrupt and the iir, receive data available indication, will be issued only if the fifo has reached its programmed trigger level. they will be cleared as soon as the fifo drops below its trigger level b. the receiver line status interrupt has higher priority over the received data available interrupt c. the time-out timer will be reset after receiving a new character or after the host reads the rcvr fifo whenever a time-out interrupt occurs. the timer will be reset when the host reads one character from the rcvr fifo
IT8673F 84 rcvr fifo time-out interrupt: by enabling the rcvr fifo and receiver interrupts, the rcvr fifo time-out interrupt will occur under the following conditions: a. the rcvr fifo time-out interrupt will occur only if there is at least one character in the fifo whenever the interval between the most recent received serial character and the most recent host read from the fifo is longer than four consecutive character times b. the rlck clock signal input is used to calculate character times c. the time-out timer will be reset after receiving a new character or after the host reads the rcvr fifo whenever any time-out interrupt occurs. the timer will be reset when the host reads one character from the rcvr fifo (2) xmit interrupt by setting fcr(0) and ier(1) to high, the xmit fifo and transmitter interrupts are enabled, and the xmit interrupt occurs under the conditions described below: a. the transmitter interrupt occurs when the xmit fifo is empty, and it will be reset if the thr is written or the iir is read. b. the transmitter fifo empty indications will be delayed one character time minus the last stop bit time whenever the following condition occurs: thre = 1 and there have not been at least two bytes in the transmitter fifo at the same time since the last thre = 1. the transmitter interrupt after changing fcr(0) will be immediate, if it is enabled. once the first transmitter interrupt is enabled, the thre indication is delayed one character time minus the last stop bit time. the character time-out and rcvr fifo trigger level interrupts are in the same priority order as the received data available interrupt. the xmit fifo empty is in the same priority as the transmitter holding register empty interrupt. fifo polled mode operation [fcr(0)=1, and ier(0), ier(1), ier(2), ier(3) or all are ?0?] either or both xmit and rcvr can be in this operation mode. the operation mode can be programmed by users and is responsible for checking the rcvr and xmit status via the lsr described below: lsr(7): rcvr fifo error indication lsr(6): xmit fifo and shift register empty lsr(5): the xmit fifo empty indication lsr(4) - lsr(1): specify that errors have occurred. character error status is handled in the same way as in the interrupt mode. the iir is not affected since ier(2)=0. lsr(0): this bit is high whenever the rcvr fifo contains at least one byte. no trigger level is reached or time-out condition indicated in the fifo polled mode.
IT8673F 85 11.6 parallel port the IT8673F supports the ibm at, ps/2 compatible bi-directional standard parallel port (spp), the enhanced parallel port (epp) and the extended capabilities port (ecp). refer to the IT8673F configuration registers and hardware configuration description for information on the following: enabling/disabling, changing the base address of the parallel port, and operation mode selection. table 11-37. parallel port connector in different modes host connector pin no. spp epp ecp 1 96 stb# write# nstrobe 2-9 91-84 pd0 - 7 pd0 - 7 pd0 - 7 10 82 ack# intr nack 11 81 busy wait# busy periphack(2) 12 80 pe (nu) (1) perror nackreverse(2) 13 79 slct (nu) (1) select 14 95 afd# dstb# nautofd hostack(2) 15 94 err# (nu) (1) nfault nperiphrequest(2) 16 93 init# (nu) (1) ninit nreverserequest(2) 17 92 slin# astb# nselectin notes : 1. nu : not used 2. fast mode 3. for more information, please refer to the ieee 1284 standard.
IT8673F 86 11.6.1 spp and epp modes table 11-38. address map and bit map for spp and epp modes register address i/o d0 d1 d2 d3 d4 d5 d6 d7 mode data port base+0h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 spp/epp status port base+1h r tmout 1 1 err# slct pe ack# busy# spp/epp control port base+2h r/w stb afd init slin irqe pddir 1 1 spp/epp epp address port base+3h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port0 base+5h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port1 base+5h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port2 base+6h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port3 base+7h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp note 1. the base address depends on the logical device conf iguration registers of parallel port (0x60, 0x61). (1) data port (primary base address + 00h) this is a bi-directional 8-bit data port. the direction of data flow is determined by the bit 5 of the logic state of the control port register. it forwards directions when the bit is low and reverses directions when the bit is high. (2) status port (primary base address + 01h) this is a read only register. writing to this register has no effects. the contents of this register are latched during an ior cycle. bit 7 - busy#: inverse of printer busy signal, a logic "0" means that the printer is busy and cannot accept another character. a logic "1" means that it is ready to accept the next character. bit 6 - ack#: printer acknowledge, a logic "0" means that the printer has received a character and is ready to accept another. a logic "1" means that it is still processing the last character. bit 5 - pe: paper end, a logic "1" indicates the paper end. bit 4 - slct: printer selected, a logic "1" means that the printer is on line. bit 3 - err#: printer error signal, a logic "0" means an error has been detected. bits 1, 2: reserved, these bits are always "1" when read. bit 0 - tmout: this bit is valid only in epp mode and indicates that a 10-msec time-out has occurred in epp operation. a logic "0" means no time-out occurred and a logic ?1? means that a time-out error has been detected. this bit is cleared by a reset or by writing a logic ?1? to it. when the IT8673F are selected to non-epp mode (spp or ecp), this bit is always logic "1" when read. (3) control port (primary base address +02h) this port provides all output signals to control the printer. the register can be read and written. bits 7, 6 : reserved, these two bits are always "1" when read. bit 5 pddir: data port direction control, this bit determines the direction of the data port. set this bit "0" to output the data port to pd bus and "1" to input from pd bus. bit 4 irqe: interrupt request enable, setting this bit "1" enables the interrupt requests from the parallel port to the host. an interrupt request is generated by a "0" to "1" transition of the ack# signal. bit 3 slin: inverse of slin# pin, setting this bit to "1" selects the printer. bit 2 init: initiate printer, setting this bit to "0" initializes the printer. bit 1 afd: inverse of the afd# pin, setting this bit to "1" causes the printer to automatically feed after each
IT8673F 87 line is printed. bit 0 stb: inverse of the stb# pin, this pin controls the data strobe signal to the printer. (4) epp address port (primary base address + 03h) the epp address port is only available in the epp mode. when the host writes to this port, the contents of d0 -d7 are buffered and output to pd0 - pd7. the leading edge of iow causes an epp address write cycle. when the host reads from this port, the contents of pd0 - pd7 are read. the leading edge of ior causes an epp address read cycle. (5) epp data ports 0-3 (primary base address + 04h - 07h) the epp data ports are only available in the epp mode. when the host writes to these ports, the contents of d0 - d7 are buffered and output to pd0 - pd7. the leading edge of iow causes an epp data write cycles. when the host reads from these ports, the contents of pd0 - pd7 are read. the leading edge of ior causes an epp data read cycle. 11.6.2 epp operation when the parallel port of the IT8673F is selected to be in the epp mode, the spp mode is also available. address/data port address is decoded (base address + 03h- 07h), the pd bus is in the spp mode, and the output signals such as stb#, afd#, init#, and slin# are set by spp control port. the direction of the data port is controlled by the bit 5 of the control port register. a 10-msec time is required to prevent the system from lockup. the time has elapsed from the beginning of the iochrdy high (epp read/write cycle) to wait# being deasserted. if a time-out occurs, the current epp read/write cycle is aborted and a logic "1" will be read in the bit 0 of the status port register. the host must write 0 to bits 0, 1, 3 of the control port register before any epp read/write cycle (epp spec.) the pins stb#, afd# and slin# are controlled by hardware for the hardware handshaking during epp read/write cycle. (1) epp address write 1. the host writes a byte to the epp address port (base address + 03h). the chip drives d0 - d7 onto pd0 - pd7. 2. the chip drives iochrdy low and asserts write (stb#) and astb# (slin#) after iow is active. 3. peripheral deasserts wait#, indicating that the chip may begin the termination of this cycle. the chip then deasserts astb#, latches the address from d0 - d7 to pd bus and releases iochrdy, allowing the host to complete the i/o write cycle. 4. peripheral asserts wait#, indicating that it acknowledges the termination of the cycle. the chip then deasserts write to terminate the cycle.
IT8673F 88 (2) epp address read 1. the host reads a byte from the epp address port. the chip drives the pd bus to tri-state for the peripheral to drive. 2. the chip drives iochrdy low and asserts astb# after ior is active. 3. peripheral drives the pd bus valid and deasserts wait#, indicating that the chip may begin to terminate this cycle. the chip then deasserts astb#, latches the address from pd bus to d0 -d7 and releases iochrdy, allowing the host to complete the i/o read cycle. 4. peripheral drives the pd bus to tri-state and then asserts wait#, indicating that it acknowledges the termination of the cycle. (3) epp data write 1. the host writes a byte to the epp data port (base address +04h - 07h). the chip drives d0- d7 onto pd0 -pd7. 2. the chip drives iochrdy low and asserts write# (stb#) and dstb#(afd#) after iow becomes active. 3. the peripheral deasserts wait#, indicating that the chip may begin the termination of this cycle. the chip then deasserts dstb#, latches the data from d0 - d7 to the pd bus and releases iochrdy, allowing the host to complete the i/o write cycle. 4. the peripheral asserts wait#, indicating that it acknowledges the termination of the cycle. the chip then deasserts write to terminate the cycle. (4) epp data read 1. the host reads a byte from the epp data port. the chip drives pd bus to tri-state for peripheral to drive. 2. the chip drives iochrdy low and asserts dstb# after ior is active. 3. the peripheral drives pd bus valid and deasserts wait#, indicating that the chip may begin the termination of this cycle. the chip then deasserts dstb#, latches the data from pd bus to d0 - d7 and releases iochrdy allowing the host to complete the i/o read cycle. 4. the peripheral tri-states the pd bus and then asserts wait#, indicating that it acknowledges the termination of the cycle. 11.6.3 ecp mode this mode is both software and hardware compatible with the existing parallel ports, allowing ecp to be used as a standard lpt port when ecp is not required. it provides an automatic high-burst-bandwidth channel that supports dma or ecp mode in both forward and reverse directions. a 16-byte fifo is implemented in both forward and reverse directions to smooth data flow and enhance the maximum bandwidth allowed. the port supports an automatic handshaking for the standard parallel port to improve compatibility and increase the speed of mode transfer. it also supports run-length encoded (rle) decompression in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times a byte has been repeated. the IT8673F does not support hardware rle compression. please refer to "extended capabilities port protocol and isa interface standard" for a detailed description.
IT8673F 89 table 11-39. bit map of the ecp registers register d7 d6 d5 d4 d3 d2 d1 d0 data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field dsr nbusy nack perror select nfault 1 1 1 dcr 1 1 ppdir irqe selectin ninit autofd strobe cfifo parallel port data fifo ecpdfifo ecp data fifo tfifo test fifo cnfga 0 0 0 1 0 0 0 0 cnfgb 0 intrvalue 0 0 0 0 0 0 ecr mode nerrintren dmaen serviceintr full empty (1) ecp register definitions table 11-40. ecp register definitions name address i/o ecp mode function data primary base +0h r/w 000-001 data register ecpafifo primary base +0h r/w 011 ecp fifo (address) dsr primary base +1h r/w all status register dcr primary base +2h r/w all control register cfifo secondary base +0h r/w 010 parallel port data fifo ecpdfifo secondary base +0h r/w 011 ecp fifo (data) tfifo secondary base +0h r/w 110 test fifo cnfga secondary base +0h r 111 configuration register a cnfgb secondary base +1h r/w 111 configuration register b ecr secondary base +2h r/w all extended control register note 1: the primary base address is selected by configurat ion registers (0x60, 0x61). the secondary base address is selected by configuration registers (0x62, 0x63). (2) ecp mode descriptions table 11-41. ecp mode descriptions mode description 000 standard parallel port mode 001 ps/2 parallel port mode 010 parallel port fifo mode 011 ecp parallel port mode 110 test mode 111 configuration mode note : please refer to the ecp register description from page 106 to 107 for detailed descripti ons of the mode selection.
IT8673F 90 (3) ecp pin descriptions table 11-42. ecp pin descriptions name type description nstrobe (hostclk) o used for handshaking with busy to write data and addresses into the peripheral device. pd0-pd7 i/o address or data or rle data. nack (periphclk) i used for handshaking with nautofd to transfer data from the peripheral device to the host. busy (periphack) i the peripheral uses this si gnal for flow control in the forward direction (hand-shaking with nstrobe). in the revers e direction, this signal is used to determine whether a command or data in formation is present on pd0-pd7. perror (nackreverse) i used to acknowledge ninit from the peripheral which drives this signal low, allowing the host to drive the pd bus. select i printer on-line indication. nautofd (hostack) o in the reverse direction, it is used for handsha king between the nack and the host. when it is asserted, a peripheral data byte is requested. in the forward direction, this signal is used to determine whether a command or data information is present on pd0-pd7. nfault (nperiphrequest) i in the forward direction (only), the peripher al is allowed (but no t required) to assert this signal (low) to request a reverse transfer while in ecp mode. the signal provides a mechanism for peer-to-peer co mmunication. it is typically used to generate an interrupt to the host, which has the ultimate control over the transfer direction. ninit (nreverserequest) o the host may drive this signal low to plac e the pd bus in the reverse direction. in the ecp mode, the peripheral is permitted to drive the pd bus when ninit is low and nselectin is high. nselectin (1284 active) o always inactive (high) in the ecp mode. (4) data port (primary base+0h, modes 000 and 001) its contents will be cleared by a reset. in a write operation, the contents of the data bus are latched by data register at the rising edge of the iow# input. the contents are then sent without being inverted to pd0-pd7. the contents of data ports are read and sent to the host in a read operation. (5) ecpafifo port (address/rle) (primary base+0h, mode 011) any data byte written to this port are placed in the fifo and tagged as an ecp address/rle. the hardware then sends this data automatically to the peripheral. the operation of this port is only valid in forward direction (dcr(5)=0).
IT8673F 91 (6) device status register (dsr) (primary base+1h, mode all) bits 0, 1 and 2 of this register are not implemented. these bit states remain at high in a read operation of printer status register. dsr(7):this bit is the inverted level of the busy input. dsr(6): this bit is the state of the nack input. dsr(5): this bit is the state of the perror input. dsr(4): this bit is the state of the select input. dsr(3): this bit is the state of the nfault input. dsr(2)-dsr(0): these bits are always 1. (7) device control register (dcr) (primary base+2h, mode all) bits 6 and 7 of this register supply no function. they are set high during the read operation, and cannot be written. contents in bits 0-5 are initialized to 0 when the reset pin is active. dcr(7)-dcr(6) : these two bits are always high. dcr(5) : except in modes 000 and 010, setting this bit low means that the pd bus is in output operation; setting it high, in input operation. this bit will be forced low in mode 000. dcr(4): setting this bit high enables the interrupt request from the peripheral to the host due to a rising edge of the nack input. dcr(3): it is inverted and output to the pin nselectin. dcr(2): it is output to the pin ninit without inversion. dcr(1): it is inverted and output to the pin nautofd. dcr(0): it is inverted and output to the pin nstrobe. (8) parallel port data fifo (cfifo) (secondary base+0h, mode 010) bytes written or dma transferred from the host to this fifo are sent by a hardware handshaking to the peripheral according to the standard parallel port protocol. this operation is only defined for the forward direction. (9) ecp data fifo (ecpdfifo) (secondary base+0h, mode 011) when the direction bit dcr(5) is 0, bytes written or dma transferred from the host to this fifo are sent by a hardware handshaking to the peripheral according to the ecp parallel port protocol. when the dcr(5) is 1, data bytes from the peripheral to this fifo are read in an automatic hardware handshaking. the host can acquire these bytes by performing read operations or dma transfers from this fifo. (10) test fifo mode (tfifo) (secondary base+0h, mode 110) the host may operate read/write or dma transfers to this fifo in any direction. data in this fifo will be displayed on the pd bus without using hardware protocol handshaking. the tfifo will not accept new data after it is full. performing a read operation from an empty tfifo causes the last data byte to return. (11) configuration register a (cnfga) (secondary base+0h, mode 111) this read only register indicates to the system that interrupts are isa-pulses. this is an 8-bit implementation by returning a 10h.
IT8673F 92 (12) configuration register b (cnfgb) (secondary base+1h, mode 111) this register is read only . cnfgb(7): a logic ?0? read indicates that the chip does not support hardware rle compression. cnfgb(6):returns the value on the isa irq line to warn possible conflicts. cnfgb(5)-cnfgb(3): a value 000 read indicates that the interrupt must be selected with jumpers. cnfgb(2)-cnfgb(0): a value 000 read indicates that the dma channel is a jumpered 8-bit dma. (13) extended control register (ecr) (secondary base+2h, mode all) table 11-43. extended control register (ecr) mode and description ecr mode and description 000 standard parallel port mode. the fifo is reset and the dire ction bit dcr(5) is always ?0? (forward direction) in this mode. 001 ps/2 parallel port mode. it is similar to the spp mode except that the dcr(5) is read/write . when dcr(5) is ?1?, the pd bus is tri-state. reading the data port returns t he value on the pd bus instead of the value of the data register. 010 parallel port data fifo mode. this mode is similar to the 000 mode, except that the host writes or dma transfers the data bytes to the fifo. the fifo data is then automatically sent to the peripheral using the standard parallel port protocol. this mode is only valid in the forward direction (dcr(5)=0) 011 ecp parallel port mode. in the forward direction, byte s placed into the ecpdfifo and ecpafifo are stored in a single fifo and automatically sent to the peripheral under the ecp protocol. in the reverse direction, bytes are sent to the ecpdfifo from ecp port. 100, 101 reserved, not defined. 110 test mode. in this mode, the fifo may be read from or written to, but it cannot be sent to the peripheral. 111 configuration mode. in this mode , the cnfga and cnfgb registers are accessible at 0x400 and 0x401.
IT8673F 93 ecp function control register. ecr(7)-ecr(5): these bits are used for read/write and mode selection. ecr(4): nerrintren, read/write , valid in ecp(011) mode 1: disables the interrupt generated on the asserting edge of the nfault input. 0: enables the interrupt pulse on the asserting e dge of the nfault. an interrupt pulse will be generated if nfault is asserted, or if this bit is written from ?1? to ?0? in the low level nfault. ecr(3): dmaen, read/write 1: enables dma. dma starts when serviceintr (ecr(2)) is 0. 0: disables dma unconditionally. ecr(2): serviceintr, read/write 1: disables dma and all service interrupts. 0: enables the service interrupts. this bit will be set to 1 by hardware when one of the three service interrupts has occurred. writing ?1? to this bit will not generate an interrupt. case 1: dmaen=1 during dma, this bit is set to ?1? (a service interrupt generated) if the terminal count is reached. case 2: dmaen=0, dcr(5)=0 this bit is set to ?1? (a service interrupt generated) whenever there is writeiintrthreshold or more space-free bytes in the fifo. case 3: dmaen=0, dcr(5)=1 this bit is set to 1 (a service interrupt generated) whenever there is readintrthreshold or more valid bytes to be read from the fifo. ecr(1): full, read only 1: the fifo is full and cannot accept another byte. 0: the fifo has at least one free data byte space. ecr(0): empty, read only 1: the fifo is empty. 0: the fifo contains at least one data byte. (14) mode switching operation in programmed i/o control (mode 000 or 001), p1284 negotiation and all other tasks happening before data are transferred, and are controlled by software. setting mode to 011 or 010 will cause the hardware to perform an automatic control-line handshaking and transferring information between the fifo and the ecp port. from mode 000 or 001, any other mode may be immediately switched to or any other mode. to change directions, the mode must first be set to 001. in extended forward mode, the fifo must be cleared and all signals deasserted before returning to mode 000 or 001. in the ecp reverse mode, all data must be read from the fifo before returning to mode 000 or 001. unneeded data are usually accumulated during ecp reverse handshaking, as when the mode is changed during a data transfer. if the above condition is satisfied, nautofd will be deasserted regardless
IT8673F 94 of the transfer state. to avoid bugs during handshaking, these guidelines must be followed. (15) software operation (ecp) before the ecp operation can begin, it is first necessary for the host to switch the mode to 000 to negotiate with the parallel port. host determines whether the peripheral supports the ecp protocol during the process. after the negotiation is completed, the mode is set to 011 (ecp). to enable the drivers, the direction must be set to 0. both strobe and autofd are set to 0, causing the nstrobe and nautofd signals to be deasserted. all fifo data transfers are pword wide and pword aligned. permitted only in the forward direction, address/rle transfers are byte-wide. ecp address/rle bytes may be automatically transmitted by writing to the ecpafifo. similarly, data pwords may be sent automatically via the ecpdfifo. to change directions, the host switches mode to 001. it then negotiates either the forward or reverse channel, sets direction to ?1? or ?0?, and finally switches mode to 001. if the direction is set to 1, the hardware performs a handshaking for each ecp data byte read, and tries to fill the fifo. at this time, pwords may be read from the ecpdfifo while it retains data. it is also possible for the hardware to perform the ecp transfers by handshaking with individual bytes under programmed control in mode = 001, or 000, even though this is a comparatively time-consuming approach. (16) hardware operation (dma) the standard pc dma protocol is followed. as in the programmed i/o case, the software sets direction and state. next, the desired count and memory address are programmed into dma controller. the dmaen is set to 1, and the serviceintr is set to ?0?. to complete the process, the dma channel with the dma controller is unmasked. the contents in the fifo are emptied or filled by dma using the right mode and direction. dma is always transferred to or from the fifo located at 0 x 400. by generating an interrupt and asserting a serviceintr, dma is disabled when the dma controller reaches the terminal count. by not asserting ldrq# for more than 32 consecutive dma cycles, blocking of refresh requests is eliminated. when it is necessary to disable a dma while this is performing a data transfer, the host dma controller is disabled serviceintr is then set to?1?, and dmaen is next set to 0. the dma will start again whether or not the contents in fifo are empty or full. this is done first by enabling the host dma controller, then setting dmaen to ?1?. the procedure is completed with serviceintr set to 0. upon the completion of a dma transfer in the forward direction, the software program must wait until the contents in fifo are empty and the busy line is low to ensure that all data reach the peripheral device successfully. (17) interrupts when any of the following states are reached, it is necessary to generate an interrupt. 1. serviceintr = 0, dmaen = 0, direction = 0, and the number of pwords in the fifo is greater than or equal to writeintrthreshold. 2. serviceintr = 0, dmaen = 0, direction = 1, and the number of pwords in the fifo is greater than or equal to readintrthreshold. 3. serviceintr = 0, dmaen = 1, and dma reaches the terminal count.
IT8673F 95 4. nerrintren = 0 and nfault goes from high to low or when nerrintren is set from ?1? to ?0? and nfault is asserted. 5. ackinten = 1. in current implementations of using existing parallel ports, the generated interrupt may be either edge trigger or level trigger type, making it "isa-friendly". (18) interrupt driven programmed i/o it is also possible to use an interrupt-driven programmed i/o to execute either ecp or parallel port fifos. an interrupt will occur in the forward direction when serviceintr is 0 and the number of free pwords in the fifo is equal to or greater than writeintrthreshold. if either of these conditions is not met, it may be filled with writeintrthreshold pwords. an interrupt will occur in the reverse direction when serviceintr is ?0? and the number of available pwords in the fifo is equal to readintrthreshold. if it is full, the fifo can be emptied completely in a single burst. if it is not full, only a number of pwords equal to readintrthreshold may be read from the fifo in a single burst. in the test mode, software can determine the values of writeintrthreshold, readintrthreshold, and fifo depth while accessing the fifo. any pc isa implementation that is adjusted to expedite dma or i/o transfer must ensure that the bandwidth on the isa is maintained on the interface. although the pc isa bus cannot be directly controlled, the interface bandwidth of the ecp port can be constrained to perform at the optimum speed. (19) standard parallel port in the forward direction with dma, the standard parallel port is run at or close to the permitted peak bandwidth of 500 kbytes/sec. the state machine does not examine nack, but just begins the next dma based on the busy signal.
IT8673F 96 11.7 keyboard controller (kbc) the keyboard controller is implemented using an 8-bit microcontroller which is capable of executing the 8042 instruction set. for general information, please refer to the description of the 8042 in the 8-bit controller handbook. in addition, the microcontroller can enter power-down mode by executing two kinds of power-down instructions. the 8-bit microcontroller has 256 bytes of ram for data memory and 2 kbytes of rom for the program storage. the rom codes may come from various vendors (or users), and are programmed during the manufacturing process. to assist in developing rom codes, the keyboard controller has an external access mode. in the external access mode, the internal rom is disabled and the instructions executed by the microcontroller come from an externally connected rom. keyboard controller krst* kclk kdat mclk mdat gatea20 kirq mirq t0 p26 p10 p27 t1 p23 p11 p22 p24 p25 p20 p21 figure 11-1. keyboard and mouse interface 11.7.1 host interface the keyboard controller interfaces with the system through the 8042 style host interface. the table below shows how the interface decodes the control signals. table 11-44. data register read/write controls host address(note) r/w* function 60h r read data 60h w write data, (clear f1) 64h r read status 64h w write command, (set f1)
IT8673F 97 note: these are the default values of the ldn5, 60h and 61h (data); ldn5, 62h and 63h (command). all these registers are programmable. read data: this is an 8-bit read only register. when read, the kirq output is cleared and obf flag in the status register is cleared. write data: this is an 8-bit write only register. when written, the f1 flag of the status register is cleared and the ibf bit is set. read status: this is an 8-bit read only register. refer to the description of the status register for more information. write command: this is an 8-bit write only register. when written, both f1 and ibf flags of the status register are set. 11.7.2 data registers and status register the keyboard controller provides two data registers, one is dbin for data input, the other is dbout for data output. each of the data registers are 8-bit wide. a write (microcontroller) to the dbout will load keyboard data read buffer, set obf flag and set the kirq output. a read (microcontroller) of the dbin will read the data from the keyboard data or command write buffer and clear the ibf flag. the status register holds information concerning the status of the data registers, the internal flags, and some user-defined status bits. please refer to table 11-45. the bit 0 obf is set to ?1? when the microcontroller writes a data into dbout, and is cleared when the system initiates a data read operation. the bit 1 ibf is set to ?1? when the system initiates a write operation, and is cleared when the microcontroller executes an ?in a, dbb? instruction. the f0 and f1 flags can be set or reset when the microcontroller executes the clear and complement flag instructions. f1 also holds system write information when the system performs write operations. table 11-45. status register 7 6 5 4 3 2 1 0 st7 st6 st5 st4 f1 f0 ibf obf 11.7.3 keyboard and mouse interface kclk is the keyboard clock pin; its output is the inversion of pin p26 of the microcontroller, and the input of kclk is connected to the t0 pin of the microcontroller. kdat is the keyboard data pin; its output is the inversion of pin p27 of the microcontroller, and the input of kdat is connected to the p10 of the microcontroller. mclk is the mouse clock pin; its output is the inversion of pin p23 of the microcontroller, and the input of mclk is connected to the t1 pin of the microcontroller. mdat is the mouse data pin; its output is the inversion of pin p22 of the microcontroller, and the input of mdat is connected to the p11 of the microcontroller. krst# is pin p20 of the microcontroller. gatea20 is the pin p21 of the microcontroller. these two pins are used as a software controlled or user defined outputs. external pull-ups may be required for these pins. 11.7.4 kirq and mirq kirq is the interrupt request for keyboard (default irq1), and mirq is the interrupt request for mouse (default irq12). kirq is internally connected to p24 pin of the microcontroller, and mirq is internally connected to pin p25 of the microcontroller.
IT8673F 98 11.8 consumer remote control (tv remote) ir (cir) 11.8.1 overview the cir is used in consumer remote control equipment, and is a programmable amplitude shift keyed (ask) serial communication protocol. by adjusting frequencies, baud rate divisor values and sensitivity ranges, the cir registers are able to support the popular protocols such as rc-5, nec, and recs-80. software driver programming can support new protocols. 11.8.2 features supports 30 khz-57 khz (low frequency) or 400 khz-500 khz (high frequency) carrier transmission baud rates up to 115200 bps (high frequency) demodulation optional supports transmission run-length encoding and deferral functions 32-byte fifo for data transmission or data reception 11.8.3 block diagram the cir consists of the transmitter and receiver parts. the transmitter part is responsible for transmitting data to the fifo, processing the fifo data by serialization, modulation and sending out the data through the led device. the receiver part is responsible for receiving data, processing data by demodulation, deserialization and storing data in the receiver fifo. interrupt gen. interface & registers baud rate gen. demodulator deserialization receiver fifo modulator serialization transmitter fifo transmitter receiver host interface 00000000 11110000 00000000 11110000 data data figure 11-2. cir block diagram
IT8673F 99 11.8.4 transmit operation the data written to the transmitter fifo will be exactly serialized from lsb to msb, modulated with carrier frequency and sent to the cirtx output. the data are either in bit-string format or run-length decode. before the data transmission can begin, code byte write operations must be performed to the transmitter fifo dr. the bit txrle in the tcr1 should be set to ?1? before the run-length decode data can be written into the transmitter fifo. setting txendf in the tcr1 will enable the data transmission deferral, and avoid the transmitter fifo underrun. the bit width of the serialized bit string is determined by the value programmed in the baud rate divisor registers bdlr and bdhr. when the bits hcfs and cfq[4:0] are set, either the high-speed or low-speed carrier range is selected, and the corresponding carrier frequency will also be determined. bits txmpm[1:0] and txmpw[2:0] specify the pulse numbers in a bit width and the required duty cycles of the carrier pulse according to the communication protocol. only a logic ?0? can activate the transmitter led in the format of a series of modulating pulses. 11.8.5 receive operation the receiver function is enabled if the bit rxen in the rcr is set to ?1?. either demodulated or modulated rx# signal is loaded into the receiver fifo, and the bit rxend in the rcr determines the demodulation logic should be used or not. determine the baud rate by programming the baud rate divisor registers bdlr and bdhr, and the carrier frequencies by programming the bits hcfs and cfq[4:0]. set rdwos to ?0? to sync. the bit rxact in the rcr is set to ?1? when the serial data or the selected carrier are incoming, and the sampled data will then be kept in the receiver fifo. write ?1? to the bit rxact to stop the receiver operation; ?0? to the bit rxen to disable the receiver. 11.8.6 register descriptions and address table 11-46. list of cir registers address r/w default name base + 0h r/w ffh cir data register (dr) base + 1h r/w 00h cir interrupt enable register (ier) base + 2h r/w 01h cir receiver control register (rcr) base + 3h r/w 00h cir transmitter control register 1 (tcr1) base + 4h r/w 5ch cir transmitter control register 2 (tcr2) base + 5h r 00h cir transmitter status register (tsr) base + 6h r 00h cir receiver status register (rsr) base + 5h r/w 00h cir baud rate divisor low byte register (bdlr) base + 6h r/w 00h cir baud rate divisor high byte register (bdhr) base + 7h r/w 01h cir interrupt identification register (iir)
IT8673F 100 11.8.6.1 cir data register (dr) the dr, an 8-bit read/write register, is the data port for cir. data are transmitted and received through this register. address: base address + 0h bit r/w default description 7 ? 0 r/w ffh cir data register (dr[7:0]) writing data to this register causes data to be written to the transmitter fifo. reading data from this register causes data to be received from the receiver fifo. 11.8.6.2 cir interrupt enable register (ier) the ier, an 8-bit read/write register, is used to enable the cir interrupt request. address: base address + 1h bit r/w default description 7 ? 6 - - reserved for ite use. 5 r/w 0b reset (reset) this bit is a software reset function. writing a ?1? to this bit resets the registers of dr, ier, tcr1, bdlr, bdhr and iir. this bit is then cleared to initial value automatically. 4 r/w 0b baud rate register enable function control (br) this bit is used to control the baud rate registers enable read/write function. set this bit to ?1? to enable the baud rate registers for cir. set this bit to ?0? to disabdle the baud rate registers for cir. 3 r/w 0b interrupt enable function control (iec) this bit is used to control the interrupt enable function. set this bit to ?1? to enable the interrupt request for cir. set this bit to ?0? to disable the interrupt request for cir. 2 r/w 0b receiver fifo overrun interrupt enable (rfoie) this bit is used to control receiver fifo overrun interrupt request. set this bit to ?1? to enable receiver fifo overrun interrupt request. set this bit to ?0? to disable receiver fifo overrun interrupt request. 1 r/w 0b receiver data available interrupt enable (rdaie) this bit is used to enable receiver data available interrupt request. the receiver will generate this interrupt when the data available in the fifo exceed the fifo threshold level. set this bit to ?1? to enable receiver data available interrupt request. set this bit to ?0? to disable receiver data available interrupt request. 0 r/w 0b transmitter low data level interrupt enable (tldlie) this bit is used to enable transmitter low data level interrupt request. the transmitter will generate this interrupt when the data available in the fifo are less than the fifo threshold level. set this bit to ?1? to enable transmitter low data level interrupt request. set this bit to ?0? to disable transmitter low data level interrupt request.
IT8673F 101 11.8.6.3 cir receiver control register (rcr) the rcr, an 8-bit read/write register, is used to control the cir receiver. address: base address + 2h bit r/w default description 7 r/w 0b receiver data without sync. (rdwos) this bit is used to control the sync. logic for receiving data. set this bit to ?1? to obtain the receiving data without sync. logic. set this bit to ?0? to obtain the receiving data in sync. logic. 6 r/w 0b high-speed carrier frequency select (hcfs) this bit is used to select carrier frequency between high-speed and low-speed. 0 30-58 khz (default) 1 400-500 khz 5 r/w 0b receiver enable (rxen) this bit is used to enable receiver function. enable receiver and the rxact will be active if the selected carrier frequency is received. set this bit to ?1? to enable the receiver function. set this bit to ?0? to disable the receiver function. 4 r/w 0b receiver demodulation enable (rxend) this bit is used to control the receiver demodulation logic. if the receiver device can not demodulate the correct carrier, set this bit to ?1?. set this bit to ?1? to enable receiver demodulation logic. set this bit to ?0? to disable receiver demodulation logic. 3 r/w 0b receiver active (rxact) this bit is used to control the receiver operation. this bit is set to ?0? when the receiver is inactive. this bit will be set to ?1? when the receiver detects a pulse (rxend=0) or pulse-train (rxend=1) with correct carrier frequency. the receiver then starts to sample the input data when receiver active is set. write a ?1? to this bit to clear the receiver active condition and make the receiver enter the inactive mode. 2-0 r/w 001b receiver demodulation carrier range (rxdcr[2:0]) these three bits are used to set the tolerance of the receiver demodulation carrier frequency. see table 11-48 and table 11-49.
IT8673F 102 11.8.6.4 cir transmitter control register 1 (tcr1) the tcr1, an 8-bit read/write register, is used to control the transmitter. address: base address + 3h bit r/w default description 7 r/w 0b fifo clear (fifoclr) writing a ?1? to this bit clears the fifo. this bit is then cleared to 0 automatically. 6 r/w 0b internal loopback enable (ile) this bit is used to execute internal loopback for test and must be ?0? in normal operation. set this bit to ?0? to disable the internal loopback mode. set this bit to ?1? to enable the internal loopback mode. 5 - 4 r/w 0b fifo threshold level (fifotl) these two bits are used to set the fifo threshold level. the fifo length is 32 bytes for tx or rx function (ile = 0) in normal operation and 16 bytes for both tx and rx in internal loopback mode (ile = 1). 00 01 10 11 16-byte mode 1 3 7 13 32-byte mode 1(default) 7 17 25 3 r/w 0b transmitter run length enable (txrle) this bit controls the transmitter run length encoding/decoding mode, which condenses a series of ?1? or ?0? into one byte with the bit value stored in bit 7 and number of bits minus 1 in bits 6 ? 0. set this bit to ?1? to enable the transmitter run length encoding/decoding mode. set this bit to ?0? to disable the transmitter run length encoding/decoding mode. 2 r/w 0b transmitter deferral (txendf) this bit is used to avoid transmitter underrun condition. when this bit is set to ?1?, the transmitter fifo data will be retained until the transmitter time-out condition occurs or the fifo reaches full. 1 ? 0 r/w 0b transmitter modulation pulse mode (txmpm[1:0]) these two bits are used to define the transmitter modulation pulse mode. txmpm[1:0] modulation pulse mode c_pls mode (default): pulses are generated continuously for the entire logic 0 bit time. 8_pls mode: 8 pulses are generated for each logic 0 bit. 6_pls mode: 6 pulses are generated for each logic 0 bit. 11: reserved
IT8673F 103 11.8.6.5 cir transmitter control register (tcr2) the tcr2, an 8-bit read/write register, is used to determine the carrier frequency. address: base address + 4h bit r/w default description 7 ? 3 r/w 01011b carrier frequency (cfq[4:0]) these five bits are used to determine the modulation carrier frequency. see table 11-47 on the next page. 2 ? 0 r/w 100b transmitter modulation pulse width (txmpw[2:0]) these three bits are used to set the transmitter modulation pulse width. the duty cycle of the carrier will be determined according to the settings of carrier frequency and the selection of transmitter modulation pulse width. txmpw[2:0] 000 001 010 011 100 101 110 111 hcfs = 0 reserved reserved 6 s 7 s 8.7 s 10.6 s 13.3 s reserved hcfs = 1 reserved reserved 0.7us 0.8us 0.9us(default) 1.0us 1.16us reserved
IT8673F 104 table 11-47. modulation carrier frequency cfq low frequency (hcfs =0) high frequency (hcfs = 1) 00000 27 khz - 00010 29 khz - 00011 30 khz 400 khz 00100 31 khz - 00101 32 khz - 00110 33 khz - 00111 34 khz - 01000 35 khz 450 khz 01001 36 khz - 01010 37 khz - 01011 38 khz (default) 480 khz (default) 01100 39 khz - 01101 40 khz 500 khz 01110 41 khz - 01111 42 khz - 10000 43 khz - 10001 44 khz - 10010 45 khz - 10011 46 khz - 10100 47 khz - 10101 48 khz - 10110 49 khz - 10111 50 khz - 11000 51 khz - 11001 52 khz - 11010 53 khz - 11011 54 khz - 11100 55 khz - 11101 56 khz - 11110 57 khz - 11111 58 khz -
IT8673F 105 table 11-48. receiver demodulation low frequency (hcfs = 0) rxdcr 001 010 011 100 101 110 cfq min. max. min. max. min. max. min. max. min. max. min. max. (hz) 00001 26.25 29.75 24.5 31.5 22.75 33.25 21 35 19.25 36.75 17.5 38.5 28k 00010 27.19 30.81 25.38 32.63 23.56 34.44 21.75 36.25 19.94 38.06 18.13 39.88 29k 00011 28.13 31.88 26.25 33.75 24.38 35.63 22.5 37.5 20.63 39.38 18.75 41.25 30k 00100 29.06 32.94 27.13 34.88 25.19 36.81 23.25 38.75 21.31 40.69 19.38 42.63 31k 00101 30 34 28 36 26 38 24 40 22 42 20 44 32k 00110 30.94 35.06 28.88 37.13 26.81 39.19 24.75 41.25 22.69 43.31 20.63 45.38 33k 00111 31.88 36.13 29.75 38.25 27.63 40.38 25.5 42.5 23.38 44.63 21.25 46.75 34k 01000 32.81 37.19 30.63 39.38 28.44 41.56 26.25 43.75 24.06 45.94 21.88 48.13 35k 01001 33.75 38.25 31.5 40.5 29.25 42.75 27 45 24.75 47.25 22.5 49.5 36k 01010 34.69 39.31 32.38 41.63 30.06 43.94 27.75 46.25 25.44 48.56 23.13 50.88 37k 01011 35.63 40.38 33.25 42.75 30.88 45.13 28.5 47.5 26.13 49.88 23.75 52.25 38k 01100 36.56 41.44 34.13 43.88 31.69 46.31 29.25 48.75 26.81 51.19 24.38 53.63 39k 01101 37.5 42.5 35 45 32.5 47.5 30 50 27.5 52.5 25 55 40k 01110 38.44 43.56 35.88 46.13 33.31 48.69 30.75 51.25 28.19 53.81 25.63 56.38 41k 01111 39.38 44.63 36.75 47.25 34.13 49.88 31.5 52.5 28.88 55.13 26.25 57.75 42k 10000 40.31 45.69 37.63 48.38 34.94 51.06 32.25 53.75 29.56 56.44 26.88 59.13 43k 10001 41.25 46.75 38.5 49.5 35.75 52.25 33 55 30.25 57.75 27.5 60.5 44k 10010 42.19 47.81 39.38 50.63 36.56 53.44 33.75 56.25 30.94 59.06 28.13 61.88 45k 10011 43.13 48.88 40.25 51.75 37.38 54.63 34.5 57.5 31.63 60.38 28.75 63.25 46k 10100 44.06 49.94 41.13 52.88 38.19 55.81 35.25 58.75 32.31 61.69 29.38 64.63 47k 10101 45 51 42 54 39 57 36 60 33 63 30 66 48k 10110 45.94 52.06 42.88 55.13 39.81 58.19 36.75 61.25 33.69 64.31 30.63 67.38 49k 10111 46.88 53.13 43.75 56.25 40.63 59.38 37.5 62.5 34.38 65.63 31.25 68.75 50k 11000 47.81 54.19 44.63 57.38 41.44 60.56 38.25 63.75 35.06 66.94 31.88 70.13 51k 11001 49.18 54.55 46.88 57.69 44.78 61.22 42.86 65.22 41.1 69.77 39.47 75 52k 11010 49.69 56.31 46.38 59.63 43.06 62.94 39.75 66.25 36.44 69.56 33.13 72.88 53k 11011 50.63 57.38 47.25 60.75 43.88 64.13 40.5 67.5 37.13 70.88 33.75 74.25 54k 11100 51.56 58.44 48.13 61.88 44.69 65.31 41.25 68.75 37.81 72.19 34.38 75.63 55k 11101 52.5 59.5 49 63 45.5 66.5 42 70 38.5 73.5 35 77 56k 11110 53.44 60.56 49.88 64.13 46.31 67.69 42.75 71.25 39.19 74.81 35.63 78.38 57k
IT8673F 106 table 11-49. receiver demodulation high frequency (hcfs = 1) rxdcr 001 010 011 100 101 110 cfq min. max. min. max. min. max. min. max. min. max. min. max. (hz) 00011 375 425 350 450 325 475 300 500 275 525 250 550 400k 01000 421.9 478.1 393.8 506.3 365.6 534.4 337.5 562.5 309.4 590.6 281.3 618.8 450k 01011 450 510 420 540 390 570 360 600 330 630 300 660 480k 01011 468.8 531.3 437.5 562.5 406.3 593.8 375 625 343.8 656.3 312.5 687.5 500k 11.8.6.6 cir baud rate divisor low byte register (bdlr) the bdlr, an 8-bit read/write register, is used to program the cir baud rate clock. address: base address + 5h (when br = 1) bit r/w default description 7-0 r/w 00h baud rate divisor low byte (bdlr[7:0]) these bits are the low byte of the register used to divide the baud rate clock. 11.8.6.7 cir baud rate divisor high byte register (bdhr) the bdhr, an 8-bit read/write register, is used to program the cir baud rate clock. address: base address + 6h (when br = 1) bit r/w default description 7-0 r/w 00h baud rate divisor high byte (bdhr[7:0]) these bits are the high byte of the register used to divide the baud rate clock. baud rate divisor = 115200 / baud rate ex1: 2400bps 115200 /2400 = 48 48(d) = 0030 (h) bdhr = 00(h), bdlr = 30(h) ex2: bit width = 0.565 ms 1770 bps 115200 / 1770 = 65(d) = 0041(h) bdhr = 00(h), bdlr = 0041(h) 11.8.6.8 cir transmitter status register (tsr) the tsr, an 8-bit read only register, provides the transmitter fifo status. address: base address + 5h bit r/w default description 7-6 r - reserved 5-0 r 000000b transmitter fifo byte count (txfbc[5:0]) return the number of bytes left in the transmitter fifo.
IT8673F 107 11.8.6.9 cir receiver fifo status register (rsr) the rsr, an 8-bit read only register, provides the receiver fifo status. address: base address + 6h bit r/w default description 7 r 0b receiver fifo time-out (rxfto) this bit will be set to ?1? when a receiver fifo time-out condition occurs. the conditions that must exist for a receiver fifo time-out condition to occur include the followings: a. at least one byte has been in the receiver fifo is not empty for 64 ms or more, and b. the receiver has been inactive (rxact=0) for over 64 ms or more, and c. more than 64 ms have elapsed since the last byte was read from the receiver fifo by the cpu 6 - - reserved 5 ? 0 r 000000b receiver fifo byte count (rxfbc) return the number of bytes left in the receiver fifo. 11.8.6.10 cir interrupt identification register (iir) the iir, an 8-bit read only register, is used to identify the pending interrupts. address: base address + 7h bit r/w default description 7 - 3 - - reserved 2 ? 1 r 00b interrupt identification these two bits are used to identify the source of the pending interrupts. iid[1:0] interrupt source 00 no interrupt 01 transmitter low data level interrupt 10 receiver data stored interrupt 11 receiver fifo overrun interrupt 0 r 1b interrupt pending this bit will be set to ?1? while an interrupt is pending.
IT8673F 108 12. dc electrical characteristics absolute maximum ratings* applied voltage.................................... -0.5v to 7.0v input voltage (vi) ....................... -0.5v to vcc+0.5v output voltage (vo)................. -0.5v to vcc + 0.3v operation temperature (topt)............. 0 c to +70 c storage temperature .................... -55 c to +125 c power dissipation ........................................ 300mw *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (vcc = 5v 5%, ta = 0 c to + 70 c) symbol parameter min. typ. max. unit conditions do8 buffer v ol low output voltage 0.4 v i ol = 8 ma v oh high output voltage 2.4 v i oh = -8 ma dod8 buffer v ol low output voltage 0.4 v i ol = 8 ma dod24 buffer v ol low output voltage 0.4 v i ol = 24 ma do16 buffer v ol low output voltage 0.4 v i ol = 16 ma v oh high output voltage 2.4 v i oh = -16 ma do40 buffer v ol low output voltage 0.5 v i ol = 48 ma v oh high output voltage 2.4 v i oh = -6 ma diod8 type buffer v ol low output voltage 0.4 v i ol = 8 ma v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc i oz 3-state leakage 20 a diod16 type buffer v ol low output voltage 0.4 v i ol = 16 ma v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc i oz 3-state leakage 20 a
IT8673F 109 dc electrical characteristics (vcc = 5v 5%, ta = 0 c to + 70 c) [cont?d] symbol parameter min. typ. max. unit conditions dio24 type buffer v ol low output voltage 0.4 v i ol = 24 ma v oh high output voltage 2.4 v i oh = -24 ma v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc i oz 3-state leakage 20 a di type buffer v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc
IT8673F 110 13. ac characteristics (vcc = 5v 5%, ta = 0 c to + 70 c) 13.1 clock input timings symbol parameter min. typ. max. unit t 1 clock high pulse width when clkin=48 mhz 1 8 nsec t 2 clock low pulse width when clkin=48 mhz 1 8 nsec t 3 clock period when clkin=48 mhz 1 20 21 22 nsec t 4 clock high pulse width when clkin=24 mhz 1 18 nsec t 5 clock low pulse width when clkin=24 mhz 1 18 nsec t 6 clock period when clkin=24 mhz 1 40 42 44 nsec 1. not tested in mass-production. guaranteed by design. t 1 , t 4 t 2 , t 5 t 3 , t 6 0.8v 2.2v 13.2 pciclk and reset timings symbol parameter min. typ. max. unit t 1 pciclk cycle time 1 28 nsec t 2 pciclk high time 1 11 nsec t 3 pciclk low time 1 11 nsec t 4 reset high pulse width 1.5 sec 1. not tested in mass-production. guaranteed by design. t 2 t 3 t 1 0.8v 2.2v t 4
IT8673F 111 13.3 cpu read cycle timings symbol parameter min. typ. max. unit t 1 address setup to ior# 10 nsec t 2 address hold from ior# 10 nsec t 3 ior# pulse width 100 nsec t 4 data valid to ior# 25 65 nsec t 5 output floating delay from ior# 25 50 nsec t 1 t 4 a[15-0] aen t 2 ior # d[7:0] valid data t 5 t 3 t 2 13.4 cpu write cycle timings symbol parameter min. typ. max. unit t 1 address setup to iow# 10 nsec t 2 address hold from iow# 10 nsec t 3 iow# pulse width 100 nsec t 4 data setup to iow# 25 nsec t 5 data hold from ior# 15 nsec t 1 t 4 a[15-0] aen iow # d[7:0] valid data t 5 t 3 t 2
IT8673F 112 13.5 serirq timings symbol parameter min. typ. max. unit t 1 float to active delay 3 nsec t 2 output valid delay 12 nsec t 3 active to float delay 6 nsec t 4 input setup time 9 nsec t 5 input hold time 3 nsec t 2 t 1 t 3 serirq (output) pciclk serirq (input) input valid t 5 t 4 13.6 dma timings symbol parameter min. typ. max. unit t 1 float to active delay 3 nsec t 2 output valid delay 12 nsec t 3 active to float delay 6 nsec t 4 input setup time 9 nsec t 5 input hold time 3 nsec ior# iow# t 1 t 2 ,t 3 dackx# drqx tc t 4
IT8673F 113 13.7 floppy disk drive timings symbol parameter min. typ. max. unit t 1 dir# active to step# low 4x t mclk note1 nsec t 2 step# active time (low) 24x t mclk nsec t 3 dir# hold time after step# t srt note2 msec t 4 step# cycle time t srt msec t 5 index# low pulse width 2x t mclk nsec t 6 rdata# low pulse width 40 nsec t 7 wdata# low pulse width 1x t mclk nsec note 1: t mclk is the cycle of main clock for the microcontroller of fdc. 1/ t mclk =8m/ 4m/ 2.4m/ 2m hz for 1m/ 500k/ 300k/ 250 kbps transfer rates respectively. note 2: t srt is the cycle of the step rate time. please refer to the functional description of the specify command of the fdc. dir# step# index# t 1 t 2 t 3 t 4 t 5 rdata# wdata# t 6 t 7
IT8673F 114 13.8 serial port, askir, sir and consumer remote control timings symbol parameter conditions min. max. unit transmitter t btn ? 25 note1 t btn + 25 nsec t 1 single bit time in serial port and askir receiver t btn ? 2% t btn + 2% nsec transmitter 950 1050 nsec t 2 modulation signal pulse width in askir receiver 500 nsec transmitter 1975 2025 nsec t 3 modulation signal period in askir receiver 2000x(23/24) 2000x(25/24) nsec transmitter, variable (3/16) x t btn ? 25 (3/16) x t btn + 25 nsec transmitter, fixed 1.48 1.78 sec t 4 sir signal pulse width receiver 1 sec note 1: t btn is the nominal bit time in serial port, askir, and sir. it is determined by the setting on the baud rate divisor registers. serial port sir sharp-ir consumer remote control t 1 t 2 t 3 t 4 13.9 modem control timings symbol parameter min. typ. max. unit t 1 float to active delay 40 nsec cts1#, dsr1#, dcd1#, cts2#, dsr2#, dcd2# interrupt (internal signal) ri1#, ri2# t 1 (read msr) (read msr) t 1 t 1
IT8673F 115 13.10 epp address or data write cycle timings symbol parameter min. typ. max. unit t 1 write# asserted to pd[7:0] valid 50 nsec t 2 astb# or dstb# asserted to wait# de-asserted 0 10 nsec t 3 wait# de-asserted to astb# or dstb# de-asserted 65 135 nsec t 4 astb# or dstb# de-asserted to wait# asserted 0 nsec t 5 wait# asserted to write# de-asserted 65 nsec t 6 pd[7:0] invalid after write# de-asserted 0 nsec write# astb# dstb# wait# pd[ 7:0 ] t 1 t 2 t 3 t 4 t 5 t 6 13.11 epp address or data read cycle timings symbol parameter min. typ. max. unit t 1 astb# or dstb# asserted to wait# de-asserted 10 nsec t 2 astb# or dstb# asserted to pd[7:0] hi-z 0 nsec t 3 pd[7:0] valid to wait# de-asserted 0 nsec t 4 wait# de-asserted to astb# or dstb# de-asserted 65 135 nsec t 5 astb# or dstb# de-asserted to wait# asserted 0 nsec t 6 pd[7:0] invalid after astb# or dstb# de-asserted 20 nsec write# astb# dstb# wait# pd[ 7:0 ] t 1 t 2 t 3 t 4 t 5 t 6
IT8673F 116 13.12 ecp parallel port forward timings symbol parameter min. typ. max. unit t 1 pd[7:0] and nautofd valid to nstrobe asserted 50 nsec t 2 nstrobe asserted to busy asserted 0 nsec t 3 busy asserted to nstrobe de-asserted 70 170 nsec t 4 nstrobe de-asserted to busy de-asserted 0 nsec t 5 busy de-asserted to pd[7:0] and nautofd changed 80 180 nsec t 6 busy de-asserted to nstrobe asserted 70 170 nsec pd[7:0], nautofd nstrobe busy t 1 t 2 t 3 t 4 t 5 t 6 13.13 ecp parallel port backward timings symbol parameter min. typ. max. unit t 1 pd[7:0] valid to nack asserted 0 nsec t 2 nack asserted to nautofd asserted 70 170 nsec t 3 nautofd asserted to nack de-asserted 0 nsec t 4 nack de-asserted to nautofd de-asserted 70 170 nsec t 5 nautofd de-asserted to pd[7:0] changed 0 nsec t 6 nautofd de-asserted to nack asserted 0 nsec pd[7:0] nack nautofd t 1 t 2 t 3 t 4 t 5 t 6
IT8673F 117 14. package information qfp 128l outline dimensions unit: inches/mm 39 64 d e a a 2 a 1 102 65 103 128 38 detail "a" 1 see detail "f" seating plane e 1 b d 1 e detail "a" d y 0.10 b base metal c with plating l 1 detail "f" l gage plane y dimension in inch dimension in mm symbol min. nom. max. min. nom. max. a - - 0.134 - - 3.40 a 1 0.010 - - 0.25 - - a 2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 - 0.008 0.09 - 0.20 d 0.906 0.913 0.921 23.00 23.20 23.40 d 1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.669 0.677 0.685 17.00 17.20 17.40 e 1 0.547 0.551 0.555 13.90 14.00 14.10 e 0.020 bsc 0.5 bsc l 0.029 0.035 0.041 0.73 0.88 1.03 l 1 0.063 bsc 1.60 bsc y - - 0.004 - - 0.10 0 - 7 0 - 7 notes: 1. dimensions d 1 and e 1 do not include mold protrusion. but mold mismatch is included. 2. dimensions b does not include dambar protrusion. 3. controlling dimension: millimeter
IT8673F 118 15. ordering information part no. package IT8673F 128l qfp

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